Semiconductor Packaging Technology

Polvimide-Metal Interfaces. Several technological applications including semiconductor packaging and metallization demand a reliable and durable adhesion properties of the metal films. In the development of multilayer devices consist of alternating layers of metal and polyimides several reliable techniques are needed to study both thin films and their interfaces. The usefulness of the nuclear scattering techniques to study the metallization and the associated interfacial elemental diffusion processes under the effects of various temperature and humidity treatments on the metal-polyimide systems, such as Al, Cu, N, and Au on Du Pont Kapton type H have already been reported (21., 22.). Only a couple of examples are presented here to illustrate the ERD application. 

Semiconductor Packaging Cu Metallization and Flip-Chip Technology... 

XyFlexPro / Speedline Technologies (7100) 13 X 10 (7200) 19 X 22 1.0 Single-head dispenser/ 30,000-120,000 (application dependent) Semiconductor packaging or surface mount SMD adhesive Amic[Pg.234]

Historically, packaging technology was developed by the integrated circuit (IC) industry. When semiconductor microdevices such as transistors are fabricated on a semiconductor wafer, electrical signals can only be accessed through many micrometersized metal lines and contacts using specialized... 

Photoresists and electron-beam resists are the key to the success of VLSI electronic circuits. Without these resists, most electronic equipment would not exist. These polymers are spun onto the semiconductor and exposed to the circuit pattern leading to main chain scission or crosslinking. Subsequently, unpolymerised sections are removed. This process is employed either in wet or in dry conditions. This is known as the photolithographic process, which is part of the semiconductor fabrication technology. Further treatment includes diffusion of various semiconductor elements and metallisation for conduction lines. Layer by layer, the total package is developed. Current research is now directed toward finer features in the patterns and changes in the surface characteristics for subsequent layers. 

The method of deposition is what differentiates the hybrid circuit from other packaging technologies and may be one of two types thick film or thin film. Other methods of metallizing a ceramic substrate, such as direct bond copper, active metal brazing, and plated copper, may also be considered to be in the hybrid family, but do not have a means for directly fabricating resistors and are not considered here. Semiconductor technology provides the active components, such as integrated circuits, transistors, and diodes. The passive components, such as resistors, capacitors, and inductors, may also be fabricated by thick- or thin-film methods or may be added as separate components. 

Carpenter, Karen, IBM Packaging Technology Keeping Pace with Semiconductor Roadmap, IBM Microelectronics MicroNews, Vol. 4, No. 4, 1998, available online at http //www.chips.ibm.com/ micronews/vol4 no4/packaging.html. 

When solder mask is used on substrates that will become part of a semiconductor package. The JEDEC Solid State Technology Association (once known as the Joint Electron Device Engineering Council) specifications apply in addition to the IPC specifications. JEDEC specifications include additional, more aggressive testing that generally requires a more robust solder mask. Low moisture absorption is important for a mask used in packaging apphcations. 

Key to the understanding of environmental, health and safety issues in the semiconductor industry i s an understanding ofthe chemicals used in the manufacture and packaging of semiconductors and semiconductor related technologies. Chapters, Chemical Hazards in Semiconductor Operations, co-authored by Tom Hawkinson and Daryl Korpela offers an overview ofthe types of ehemieals used in the semiconductor industry as well as the related processes. 

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