Semiconductor interconnection fabrication

This topic is well covered by the contributions in this volume. CMP continues to be viewed as a surprisingly unique and flexible semiconductor fabrication technology by virtue of its ability to make manufactureable potential fabrication sequences that are either too cumbersome or too low in yield to be fabricated in any other manner. Using virtually any CMP polisher, a variety of materials of interest to IC fabricators can be planarized. These materials include insulators, semiconductors, interconnect metals, and barrier metallurgies. This means that once a user becomes adept in polishing one kind of material, typically oxide and W at first, other materials of interest and other semiconductor processing sequences become viable. 

In tape-automated bonding (TAB), the semiconductor die, fabricated with bumped interconnect pads, are positioned in apertures of a polymer-film tape, generally polyimide (Kapton , a registered trademark of DuPont), then gang-bonded to cantilevered beams that are formed by photodelineated metal pads on the tape. The tape (film) has sprocket holes along its sides similar to movie film and, like movie film, is handled on reels in automatic equipment for high-speed assembly. ... 

Interconnect. Three-dimensional structures require interconnections between the various levels. This is achieved by small, high aspect-ratio holes that provide electrical contact. These holes include the contact fills which connect the semiconductor silicon area of the device to the first-level metal, and the via holes which connect the first level metal to the second and subsequent metal levels (see Fig. 13.1). The interconnect presents a major fabrication challenge since these high-aspect holes, which may be as small as 0.25 im across, must be completely filled with a diffusion barrier material (such as CVD titanium nitride) and a conductor metal such as CVD tungsten. The ability to fill the interconnects is a major factor in selecting a thin-film deposition process. 

In the fabrication of semiconductors, CVD is an important technique for the thin-film formations with an increase in device intensity performance. Tungsten hexafluoride has been widely used as a source gas of tungsten silicide (WSi,v) and tungsten metal for electrodes and interconnects. 

As mentioned in Chapter 1, the present state of CMP is the result of the semiconductor industry s needs to fabricate multilevel interconnections for increasingly complex, dense, and miniaturized devices and circuits. This need is related to improving the performance while adding more devices, functions, etc. to a circuit and chip. This chapter, therefore, discusses the impact of advanced metallization schemes on the performance and cost issues of the ICs. Our discussions start with the impact of reducing feature sizes on performance and the need of various schemes to counter the adverse effect of device shrinkage on the performance of interconnections. An impact of continued device shrinkage on circuit delay is discussed. Then the need of low resistivity metal, low dielectric constant ILD, and planarized surfaces is established leading to the discussion of CMP. Finally various planarization techniques are compared to show why CMP is the process that will satisfy the planarity requirements of the future. 

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