RISC architecture

K. Dowd, High Performance Computing RISC Architectures, Optimization, and Benchmarks, O Reilly and Associates, Sebastopol, CA, 1993. 

A newer measure of an algorithm s theoretical performance is its Mop-Cost which is defined exactly as the Flop-cost except that Memory Operations (Mops) are counted instead of Floating-Point Operations (Flops). A Mop is a load from, or a store to, fast memory. There are sound theoretical reasons why Mops should be a better indicator of practical performance than Flops, especially on recent computers employing vector or RISC architectures, and this has been discussed in detail by Frisch et al. [62] to cut a long story short, the Mops measure is useful because, on modern computers and in contrast to older ones, memory traffic generally presents a tighter bottleneck than floating-point arithmetic. 

The mid-range workstations offer 10 to 15 MIPS performance, with numeric processing at 1 to 2 MFLOPS, drawing rates of 200,000 to 400,0(X) v/s and 20,000 p/s. Their higher performance arises from so-call RISC architecture (Reduced Instruction Set CPU), which allow the computer to perform fewer tasks per CPU instruction. They also utilize faster, proprietary graphics display processors and larger display memory, which allows more colors and multiple windows. These units cost between 30,000 and 70,000, and they probably make up the bulk of recent CAMD woikstation purchases. They are suitable for solid model display and manipulation of small molecules, and wireframe and dot-surface display of macromolecules. Molecular mechanics and dynamics calcinations on small molecules and ensembles can be run in batch mode on these machines, and the results can be displayed and manipulated interactively. 

LeeR, Mahon M, Morris D (1992) Path length reduction features in the PA-RISC architecture. In Proceedings of IEEE Compcon, San Francisco, CA, 24-28 Feb 1992, pp 129-135... 

One reason that RISC architectures work better than traditional CISC machines is due to the use of large on-chip caches and register sets. Since locality of reference effects (described in the section on memory hierarchy) dominate most instruction and data reference behavior, the use of an on-chip cache and large register sets can reduce the number of instructions and data fetched per instruction execution. Most RISC machines use pipelining to overlap instruction execution, further reducing the clock period. Compiler techniques are used to exploit the natural parallelism inherent in sequentially executed programs. 

VLSI RISC Architecture and Organization, Stephen B. Furber... 

Eor all the excitement and enthusiasm of the computer architects, these computers did not meet with great success in the marketplace, and few companies remain as viable entities. One of the primary reasons for their demise seems to have been the simultaneous rise of the RISC work stations, which killed off numerous other architectural initiatives, hence the term killer micros (11). 

A recent victim of the killer micros was Evans and Sutherland s parallel computer development effort, halted ia 1990. Their architecture combiaed a small number of approximately 1-MFLOPS processors iato semi-iadependent functional units. Several of these units could, ia turn, be combiaed to form a processor hierarchy, building up to systems that were expected to cost between 1 and 8 million dollars. With the advent of lO-MFLOPS uniprocessor killer micros, such an architecture became irrelevant and the project was halted. The RISC killer micro could deUver the same level of performance as could the combiaed efforts of 10 of the 1-MFLOPS processors, evea with the unlikely assumptioa that the problem could be perfectiy parallelized across 10 processors. 

Merced The next-generation Intel architecture. Expected in the 2000-2001 time frame, it introduces the 64-bit IA-64 instruction set jointly designed by Intel and FIP, which runs x86 and PA-RISC software natively. Clock speeds are expected to go to 600MHz and beyond. 

The case study processor used in this work is based in the Microprocessor without Interlocked Pipeline Stages (MIPS) architecture. It has a standard processor architecture based on the Reduced Instraction Set Computing (RISC) instmction set. The basic idea behind RISC is to use simple instructions, which enable easier pipelining and larger caches, while increasing its performance. The MIPS architecture can be seen since 1985 in commercial applications, from workstations to Windows CE devices, routers, gateways and PlayStation gaming devices. 

The major development efforts for RISC processors were led by the University of California at Berkeley and the Stanford University designs. Sun Microsystems developed the Berkeley version of the RISC processor [scalable processor architecture (SPARC)] for their high-speed workstations. This, however, was not the first RISC processor. It was preceeded by the MIPS R2000 (based on the Stanford University design), the Hewlett Packard PA-RISC CPU, and the AMD 29000. 

RISC Reduced instruction set computer (RISC) is a type of microprocessor architecture that utilizes a small, highly-optimized set of instructions in one cycle execution time. So, RISC processors have clock per cycle instruction. A few characteristic features shall include but are not limited to ... 

MIPS (originally an acronym for microprocessor without interlocked pipeline stages) is a RISC instmction set architecture (ISA) developed by MIPS Technologies (formerly MIPS Computer Systems, Inc.) (Definition from Wikipedia). MPIS in FPGA has been covered in Clause 3.2. 

In FPGA applications, MIPS has been utilized to improve performance of the system. MIPS has RISC (see Clause 3.0.1) microprocessor architecture and defines large numbers of 32-bit GPRs. The CPU uses byte addressing for word and a byte boundary divisible by four. There are three types of instructions listed as follows, and each instruction has different format as shown in Fig. APV/3.2.4-1A. 

I-type-load and stores instmctions As MIPS is based on RISC processor it is load/store type architecture, meaning that all operations are performed on operands in the processor registers. The main memory is only accessed through the load/store instmctions which are used to load a value in to register from memory or store a value from register to memory respectively. 

V.P. Rubio, ]. Cook. A FPGA Implementation of a MIPS RISC Processor for Computer Architecture Education New Mexico State University, July 2004. http //www.ece.nmsu.edu/ jecook/thesis/Victor thesis.pdf. 

Most recent minicomputer enhancements are attributable to technology improvements, breakthroughs in compiler design, and significant improvements to the processor architecture. The minicomputer of 2000 evolved with technological advances such as evolution from the Complicated Instruction Set Computer (CISC) to the Reduced Instruction Set Computer (RISC), pipelining,... 

The proportion of vector processors in the present-day supercomputer arena is declining rapidly. The reason is the relatively small number of these systems, with their specialized processor architecture, that can be sold. This makes it impossible to amortize the high development and fabrication costs over a large user community. Therefore, nowadays these systems are often replaced by RISC-based parallel machines with a lower effective performance per processor but with more less costly processors. 

In RISC (reduced instruction set computer) research, an efficient technique has been proposed to enhance the utilization of both function units and buses. Fig 3 shows the timing diagram of such an architecture. Data transfer operations (read or write) and function unit operations are performed in parallel during each control step. Therefore, the clock period is reduced to rr ax top, U + ))- However, this gain in speed is not free. Note that for each operation its three micro-operations are performed across three consecutive control steps. In order to hold the operands across the step boundary, a latch is needed in every input/output port of every function unit. 

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