Scalable processor architecture

The pKa of a compound may be estimated using ACDpKa software, which also contains a large database of measured pKa data. The use of the computer program SPARC (scalable processor architecture) for estimating the pKa of pharmaceuticals has been described by Hilal etal. (1996). 

The major development efforts for RISC processors were led by the University of California at Berkeley and the Stanford University designs. Sun Microsystems developed the Berkeley version of the RISC processor [scalable processor architecture (SPARC)] for their high-speed workstations. This, however, was not the first RISC processor. It was preceeded by the MIPS R2000 (based on the Stanford University design), the Hewlett Packard PA-RISC CPU, and the AMD 29000. 

The scalability of an SMP multicore architecture will be determined by the balance between the processor cores performance, memory performance and I/O performance. So for example, if a processor provides cores with fast instruction execution, but has limited on-chip instruction and data cache, and relatively limited bandwidth I/O to external memory, then this will be deemed to be I/O bound, and will limit the usable hardware performance of the system. 

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