Poly silicon gates

Replacement for poly silicon gates and interconnects in MOS devices. 

Figure 20.14 [13] shows a second method of converting the polygate to silicide for high-k applications. Here again, the CMOS transistors are formed with conventional poly-silicon gates. After ILDO deposition, the surface is polished back to expose the poly-silicon. Metal films are then deposited and... 

The use of polymers with a low relative permittivity, see Section 2.7, as the FET gate insulator has been found to result in higher carrier mobility and improved device performance (Veres et al., 2003). The authors developed stable semiconductive polymers, poly(triarylamines), and used them to fabricate FETs with silicon dioxide and poly(methylmethacrylate) gate insulators. Values of the carrier mobilities measured in the FETs were about 10 times smaller than those determined by TOF experiments. A dramatic increase in FET mobility was observed when a low permittivity fluoropolymer (e = 2.1) was employed as gate insulator. The FET mobilities for devices with gate insulators with relative permittivities in the range 2-18 are shown in Fig. 10.12(a). The devices were made with two different poly(triarylamines)... 

In the discussion below we limit ourselves to pure metal gates although alternatives have been proposed such as a tungsten/poly-silicon stack [Wong and Saraswat201]. It is helpful to keep the process flow as depicted in figure 8.1 in mind. 

Layers Typical materials for which CMP processes originally have been developed for microelectronic applications include various types of silicon dioxide such as thermal oxide, TEOS, HDP, BPSG, and other B- or P-doped oxide films. These films are used for various isolation purposes including interlevel dielectric (ILD), intermetal dielectric (IMD), or shallow trench isolation (STI). In addition, n- or p-doped poly-Si, which is a semiconducting material used as capacitor electrode material for DRAMS or gate electrode for MOS applications (CMOS as well as power MOS devices), also has to be polished. Metals for which CMP processes have emerged over the last 10-15 years are W for vertical interconnects (vias) and most importantly Cu as a low-resistivity replacement for aluminum interconnects, employed in the damascene or dual-damascene processing scheme. Other metals that are required for future nonvolatile memories are noble metals like Pt or Ir for which CMP processes have been explored. 

In VLSI-MOS based circuits, where doped poly-crystalline silicon (poly-Si) is used as the gate electrode, the performance of the IC is limited by the RC time delays in the poly-Si runners (see for detailed discussions Murarka86, Sachdev et al.212). The main reason for this delay is the high resistivity (500 fiftcm) of n+ doped poly-Si. In addition, the trend to a larger die size worsens the problem because these poly-Si lines become longer. 

Polycrystalline silicon thin film transistors have also been employed for the detection of DNA hybridization [16]. A mixed self-assembled monolayer of thiolated DNA probes and mercapto-hexanol was immobilized onto the gold gate of an extended gate poly-Si TFT. A shift of the I-V characteristics on the order of 300 mV was obtained upon hybridization of the immobilized probe with a fully complementary strand. The shift is independent of electrode area, so microarrays can be constructed where a known DNA probe is immobilized on each FET. The inherent miniaturization and compatibility with microfabrication technologies make the technique highly promising for the development of low-cost portable devices. 

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