Gate instantiation

Gate level primitives can be instantiated in a model using gate instantiation. The following gate level primitives are supported for synthesis. 

Delays, if any, in gate instantiations are ignored by a synthesis system. This can potentially lead to functional mismatches between the Verilog HDL model and the synthesized netlist. 

The input to the Workbench is a mixed behavioral and structural description. In Verilog, sequential behavior is described with the always statement, combinational behavior is described with the continuous assignment statement assign), and hierarchical structural is described with module definitions, and module and gate instantiations. For the purposes of the Workbench, the synthesis tools treat the always statement as a single process description of the behavior to be synthesized into a structural data path and controller. For each always statement, a separate controller and data path is generated. 

The listing 1.7 contains an extract from the Process FCS specification, showing the instantiation of Thread NL and Thread NF (without parameters) in synchronization with Processor.CPU (Rule 6). For example, ThreadJJL has three connections (Rule 5.1) output with acc c gate input 1 through synchronization with DataPort Posc and input 2 through synchronization with DataPort Poso. Also it is in synchronization with ThreadJJF for pos o input (Rule 5.II). 

Just as a Process statement identifies a behavioural style, component declarations and instantiations identify a structural style. Unlike the behavioural style, which specifies what the circuit has to do, a VHDL description in the structural style determines the operation of the circuit by the manner in which any number of functional blocks - components - are interconnected. These may contain anything from simple two-input logic gates to 16 x 16 bit multipliers. 

Figure 4.25 Two-, three- and four-input Nand gate components instantiated in STRUCTURAL .

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