Membrane wafer

In conclusion, performing a wafer balance analysis in a fuel cell not only is critical in order to determine the effectiveness of membranes wafer crossover (or drag), but it is also a very effective tool when investigating how different diffusion layers can manipulafe wafer flow and wafer management within the MEA. 

FI CU RE 4.29 A schematic illustration of the ion transport membrane (ITM) device developed and patented by Air Products and Chemicals, Inc. The supported membrane wafers are separated by spacer rings and attached to a common product withdrawal tube. (From Armstrong P. A., Stein V.E.E., Bennet D.I., Foster E.P., Ceramic Membrane Development for Oxygen Sypply to Gasification Applications, Air Products and Chemicals, Inc., Allentown, PA, 2002. With permission.)... 

Several solid state membrane wafer units are joined to form a membrane module and channels are incorporated between the wafers for mediating the air flow. 

To achieve all of the benefits of the microchanneled, flat plate design, multiple membrane wafers must be stacked together to form multiwafer modules. 

Although the principal appHcation of reverse osmosis membranes is still desalination of brackish water or seawater to provide drinking water, a significant market is production of ultrapure water. Such water is used in steam boilers or in the electronics industry, where huge amounts of extremely pure water with a total salt concentration significantly below 1 ppm are required to wash siUcon wafers. 

Fig. 7 Schematics of a nanometer scale M-A-M diode (not drawn to scale in relative thickness). Top schematic is the cross section of a silicon wafer with a nanometer scale pore etched through a suspended silicon nitride membrane. Middle and bottom schematics show a Au/SAM/Au junction formed in the pore area. (Reprinted with permission from [30])...

Micro/nanostructures generated using these and related top-down approaches are geometrically and electrically homogeneous, with layouts that can be controlled over a wide range to realize not only ribbons and wires but also bars, platelets, membranes, and other structures. The main limitations of the top-down approach are as follows (1) The composition of the fabricated objects is limited to materials that are readily available in wafer or thin-film forms, (2) the etching processes can lead to some level of roughness on the surfaces of the structures, and (3) dimensions of less than 20 nm, for other than the thickness, are difficult to obtain reliably. 

A small serial production has been set up at the Institute for Instrumental Analysis to develop and demonstrate the fabrication of the microsystem. The production can be subdivided into four phases The wafer-based formation of the fundamental structure, the packaging stage including separation, housing assembly and contact formation of the chips, the deposition of the gradient membrane and the final annealing treatment [4, 5]. 

Silicon-based pressure sensors are amongst the most common devices making use of this process. A thin low-n-doped epitaxial layer on the wafer determines an etch stop depth and thus the thickness of e.g. the pressure sensor membrane. 

The membranes of the microhotplates were released by anisotropic, wet-chemical etching in KOH. In order to fabricate defined Si-islands that serve as heat spreaders of the microhotplate, an electrochemical etch stop (ECE) technique using a 4-electrode configuration was applied [109]. ECE on fully processed CMOS wafers requires, that aU reticles on the wafers are electrically interconnected to provide distributed biasing to the n-well regions and the substrate from two contact pads [1 lOj. The formation of the contact pads and the reticle interconnection requires a special photolithographic process flow in the CMOS process, but no additional non-standard processes. 

These equations describe an unheated transistor and were verified for a device with no backside etching (no membrane). The modelling parameters were provided by the manufacturer, whereas the value of the threshold voltage was taken from wafer map data. The channel length modulation parameter. A, had to be extracted from measurement data. The discrepancy between simulated and measured source-drain saturation current, fsd,sat> for a transistor embedded in the bulk silicon was less than 1%, which confirmed the vaHdity of the model assumptions. 

The first device was a circular-shape microhotplate, which essentially consisted of CMOS-process materials (Sect. 4.1). The fabrication of this microhotplate required a minimum of post-CMOS processing steps. The electrochemical etching process used for the membrane release and the formation of the circular-shape Si island was optimized and can now be routinely apphed on wafer-level. 

With increasing water content, the ionic domains swell from 40 to 50 A in diameter and the structure of fhe membrane is fhoughf to consist of spherical ionic domains joined by cylinders of wafer dispersed in fhe polymer matrix. Within this region of wafer confenf, proton conductivify steadily increases. At > 0.5, a morphological inversion occurs in which a connected network of aggregated polymer "rods" is now surrounded by water. This network continues to swell for X, = 0.5 —> 0.9 and fhe conductivify of fhe membrane approaches the values observed for Nafion solutions. 

A number of differenf approaches have been used to try to overcome some of these disadvantages of existing membranes. One such approach is to try to prevent water loss from the proton transport pathways, thus maintaining proton conductivity above the boiling point of wafer. Typically, this is attempted by adding hydrophilic inorganic species into the membrane. Furthermore, these particles in themselves may also be capable of proton conduction. 

Zhang, Advani, and Prasad [51,52] also used microfabrication techniques in order to develop a thin, perforated copper foil and use it as a cathode DL in a PEMLC. In addition to the metal DL, an "enhancement" layer was used that consisted of a porous material locafed befween the perforated copper foil and fhe LF plate (CLP was used in fhis study). This layer improved the overall short-term performance and wafer managemenf of fhe cell. Flowever, the authors did not discuss any possible long-term issues related to contaminahon of the membrane due to the use of a copper DL. 

Another way to use silicon wafers as DLs was presented by Meyers and Maynard [77]. They developed a micro-PEMFC based on a bilayer design in which both the anode and the cathode current collectors were made out of conductive silicon wafers. Each of fhese componenfs had a series of microchannels formed on one of their surfaces, allowing fhe hydrogen and oxygen to flow through them. Before the charmels were machined, a layer of porous silicon was formed on top of the Si wafers and fhen fhe silicon material beneath the porous layer was electropolished away to form fhe channels. After the wafers were machined, the CEs were added to the surfaces. In this cell, the actual diffusion layers were the porous silicon layers located on top of the channels because they let the gases diffuse fhrough fhem toward the active sites near the membrane. 

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