Mask aligners

Includes applying photoresist, scrub dehydrate, mask align expose, develop, rinse bake. 

Figure 17. Resist images delineated with a GCA DSW 4800 mask aligner. The Ag2Se/Geo.iSeo.9/// Pi two-layer inorganic RIE PCM system was used. The HPR planarizing layer was 2.5 in thickness. ((Reproduced with permission from Ref. 27 J...

The resist formulation was spin-coated onto a silicone wafer on which a bottom antireflective coating had been previously applied and then soft-baked for 60 seconds at 90°C on a hot plate to obtain a film thickness of 1000 nm. The resist film was then exposed to i-line radiation of 365 nm through a narrowband interference filter using a high-pressure mercury lamp and a mask aligner. Experimental samples were then baked for 60 seconds at 90°C on a hot plate and developed. The dose to clear, E0, which is the dose just sufficient to completely remove the resist film after 60 seconds immersion development in 2.38% aqueous tetramethyl ammonium hydroxide, was then determined from the measured contrast curve. Testing results are provided in Table 1. 

Normally, a one-mask process was employed for glass etching, but for specific applications, a two-mask process was used to create the shallow channel (1-6 pm deep) and the deep channel (20-22 pm deep) [115,117]. In order to fabricate shallow (18 pm) and deep (240 pm) glass channels, they were etched separately on the bottom and top plates using two masks. Alignment was achieved during bonding... 

A crude but inexpensive alternative to the mask aligner is to physically clamp the substrate to the mask, then use a UV light box, which contains several black-light fluorescent tubes, for the exposure process. With care, this procedure can produce features in the vicinity of 5 ixm and larger, making it possible to fabricate 150 MHz SAW devices on quartz, for example. 

The main purpose of the work was to obtain more specific data on orientation and morphology features of the micro- and nanosurfaces emerging under vertices of the right comers of the mask (square-shaped) fabricated on Si (001) when etched in aqueous KOH solutions of various concentrations at various temperatures and mask alignments. 

D lithography was performed by using the contact mask aligner (Karl Suss, MA6/BA6). The channel formed by anisotropic wet etching was chosen for the channel fabrication of the pDMFC because UV light can be irradiated to the sidewall. The photograph of the fabricated pDMFC is shown in Fig. 5.5. The performance of... 

A SU8-100 photoresist solution (PRS) was used in all of the procedures. In order to make the three-layer photoresist patterns for the top master, the first layer was coated as 50 pm thick on a 100 mm diameter silicon wafer 2mL PRS was spun at 500 rpm for 10 s following at 5000 rpm for 30 s with a spin coater. The spin-coated wafer was baked at 60 °C for 10 min, and then at 95 °C for 30 min. After baking, the photomask image (Figure 4.5A) was patterned on the first layer using a UV lamp (370 nm) in a mask aligner for 30 s. On the exposed first layer without a developing step, the second layer for the profile of the ESI emitter was coated as 200 pm thick 4mF PRS was spun at 500 rpm for 20 s followed by 2000 rpm for 30 s. The wafer coated with two layers was baked at 60 °C for 20 min, and then at 95 °C for 60 min. The baked wafer was exposed with a second... 

For the next generation of submicrometer ground rules, a fourfold reduction in alignment and other errors will be necessary. Almost every type of mask aligner—contact/proximity, projection scanner, and step and repeat—is used for some of the lithography steps in the fabrication of state of the art integrated circuitry today. For a detailed description of mask alignment equipment we refer to the literature [2, 3]. 

Mask aligner for contact lithography (e.g., model Q4000 MA, Neutronix-Quintel, Morgan Hill, CA). 

Expose the spin-coated wafer to UV light using the photolithography mask and the mask aligner. The exposure time is determined by the thickness of the SU-8 ( eeNote 2). 

FIGURE 44.13 Schematic of the layout for a separation chip fabricated in standard <110>- oriented silicon with either x-shaped (I) or y-shaped (II) channel outlet, (a) Mask alignment. Reproduced from Nilsson A., et al.. Lab on a Chip, 4, 131-135, 2004. With permission from Royal Society of Chemistry, (b) Channel cross-sections. Reproduced from Nilsson A., et al.. Lab on a Chip, 4, 131-135, 2004. With permission from Royal Society of Chemistry. 

The cleaned and silanized substrates were selectively patterned by photolithography using an electrically insulating photoresist [49]. A thin SU-8 2000.5 photoresist layer was spun at 6,000 rpm, soft-baked, exposed using a MJB4 mask aligner (60-80 mJcm ), post-baked, and developed in PGMEA for 30 s [49]. The applied soft and post-bake procedure was as follows 1 min at 65 °C, 1 min at 92 °C, and 1 min at 65 °C. 

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