Interconnects surface stability

With an emphasis on scale electrical conductivity (surface stability as well), a number of new alloys have been recently developed specifically for SOFC interconnect applications. The one that has received wide attention is Crofer 22 APU, an FSS developed by Quadakkers et al. [136, 137] at Julich and commercialized by Thyssen Krupp of Germany. Crofer 22 APU, which contains about 0.5% Mn, forms a unique scale, as shown in Figure 4.6, comprised of a (Mn,Cr)304 spinel top layer and a chromia sublayer [137-139], The electrical conductivity of (Mn,Cr)304 has been reported... 

The aforementioned requirements on surface stability are typical for all exposed areas of the metallic interconnect, as well as other metallic components in an SOFC stack e.g., some designs use metallic frames to support the ceramic cell. In addition, the protection layer for the interconnect or in particular the active areas that... 

The aforementioned requirements on surface stability are typical for all exposed areas of the metallic interconnect, as well as other metallic components in a SOFC stack (e.g., some designs use metallic frames to support the ceramic cell). In addition, the protection layer for the interconnect, or in particular the active areas that interface with electrodes and are in the path of electric current, must be electrically conductive. This conductivity requirement differentiates the interconnect protection layer from many traditional surface modifications as well as nonactive areas of interconnects and other components in SOFC stacks, where only surface stability is emphasized. While the electrical conductivity is usually dominated by their electronic conductivity, conductive oxides for protection layer applications often demonstrate a nonnegligible oxygen ion conductivity as well, which leads to scale growth beneath the protection layer. With this in mind, a high electrical conductivity is always desirable for the protection layers, along with low chromium cation and oxygen anion diffusivity. 

Dehydration or Chemical Stabilization. The removal of surface silanol (Si—OH) bonds from the pore network results in a chemically stable ultraporous soHd (step F, Fig. 1). Porous gel—siHca made in this manner by method 3 is optically transparent, having both interconnected porosity and sufficient strength to be used as unique optical components when impregnated with optically active polymers, such as fiuors, wavelength shifters, dyes, or nonlinear polymers (3,23). 

Traditional alloy design emphasizes surface and structural stability, but not the electrical conductivity of the scale formed during oxidation. In SOFC interconnect applications, the oxidation scale is part of the electrical circuit, so its conductivity is important. Thus, alloying practices used in the past may not be fully compatible with high-scale electrical conductivity. For example, Si, often a residual element in alloy substrates, leads to formation of a silica sublayer between scale and metal substrate. Immiscible with chromia and electrically insulating [112], the silica sublayer would increase electrical resistance, in particular if the subscale is continuous. 

Newly developed alloys have improved properties in many aspects over traditional compositions for interconnect applications. The remaining issues that were discussed in the previous sections, however, require further materials modification and optimization for satisfactory durability and lifetime performance. One approach that has proven to be effective is surface modification of metallic interconnects by application of a protection layer to improve surface and electrical stability, to modify compatibility with adjacent components, and also to mitigate or prevent Cr volatility. It is particularly important on the cathode side due to the oxidizing environment and the susceptibility of SOFC cathodes to chromium poisoning. 

The increasing importance of multilevel interconnection systems and surface passivation in integrated circuit fabrication has stimulated interest in polyimide films for application in silicon device processing both as multilevel insulators and overcoat layers. The ability of polyimide films to planarize stepped device geometries, as well as their thermal and chemical inertness have been previously reported, as have various physical and electrical parameters related to circuit stability and reliability in use (1, 3). This paper focuses on three aspects of the electrical conductivity of polyimide (PI) films prepared from Hitachi and DuPont resins, indicating implications of each conductivity component for device reliability. The three forms of polyimide conductivity considered here are bulk electronic ionic, associated with intentional sodium contamination and surface or interface conductance. 

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