Interconnect metallic

Directed Oxidation of a Molten Metal. Directed oxidation of a molten metal or the Lanxide process (45,68,91) involves the reaction of a molten metal with a gaseous oxidant, eg, A1 with O2 in air, to form a porous three-dimensional oxide that grows outward from the metal/ceramic surface. The process proceeds via capillary action as the molten metal wicks into open pore channels in the oxide scale growth. Reinforced ceramic matrix composites can be formed by positioning inert filler materials, eg, fibers, whiskers, and/or particulates, in the path of the oxide scale growth. The resultant composite is comprised of both interconnected metal and ceramic. Typically 5—30 vol % metal remains after processing. The composite product maintains many of the desirable properties of a ceramic however, the presence of the metal serves to increase the fracture toughness of the composite. 

Roberts, B., Harms, A., and Jackson, R., Interconnect Metallization for Future Device Generations, Solid State Technology, pp. 69-78 (Feb. 1995)... 

The trend in CVD metallization is toward greater use of copper, and the refractory metals and their silicides in multilayered metallization designs, typically consisting of metal-silicide contacts, refractory-metal barriers, and copper or an aluminum alloy as the principal interconnect metal. Other metals deposited by CVD such as chromium, molybdenum, platinum, rhodium, and ruthenium are also actively considered for use as conductors. 

Metallization of contacts, vias and interconnect metals still need to formed and connected. 

This topic is well covered by the contributions in this volume. CMP continues to be viewed as a surprisingly unique and flexible semiconductor fabrication technology by virtue of its ability to make manufactureable potential fabrication sequences that are either too cumbersome or too low in yield to be fabricated in any other manner. Using virtually any CMP polisher, a variety of materials of interest to IC fabricators can be planarized. These materials include insulators, semiconductors, interconnect metals, and barrier metallurgies. This means that once a user becomes adept in polishing one kind of material, typically oxide and W at first, other materials of interest and other semiconductor processing sequences become viable. 

The final steps involve deposition of fhe interconnect metal (Figure4.25, step s). Copper is now the metal-of-choice due to its more desirable electrical resistivity, relative to A1 (1.7 dQ cm v. 2.7 xO cm, respectively) that was exclusively used in earlier ICs. Due to its low resistivity and high density, titanium nitride is an efficient barrier level that prevents surface oxidation of Cu, as well as the interdiffiision of Cu into adjacent layers. To yield the final multilayer IC shown in step t of Figure 4.25, steps p-s are repeated. Indeed, a long complex process that took weeks in the making. 

Note that the key to developing a CMP process for DBAP or polish stop layer is not a process optimized for these films alone, but a process that is optimized for the interconnection metal (or any other primary layer) or DBAP or polish stop layer, as was done in the case of A1 or TiN or A1 or Ti/TiN by Wang et al. ... 

The number of transistors per chip is increasing continuously (for a microprocessor, the total number of transistors per chip was 11, 21, and 40 M (million) for years 1997, 1999, and 2001, respectively) and the physical feature size of transistors is decreasing consequently the dimensions of interconnections (interconnects) on the chip are scaling down for example, linewidths were 0.25, 0.18, 0.15, and 0.10 pm in the years 1997, 1999, 2001, and 2006, respectively. This scaling down of interconnects on chips requires interconnect metal of high quality and better understanding of physical properties of thin films [96]. 

Kaanta et al.142 implemented tungsten for contact fill, via studs, and the first interconnect metal. The via plug was produced by the blanket etch back method. The apparent disadvantage of the higher resistivity of tungsten as the interconnect was compensated by ... 

As described, the addition of Mg to an aluminum alloy permits rapid oxidation of the alloy at elevated temperatures in an oxygen-containing atmosphere. The product is a composite composed of a matrix of interconnected A1203 with a small fraction of residual A1 alloy dispersed in the matrix as interconnected metal channels. From a thermodynamic or phase diagram viewpoint, three distinct oxides can form when an Al-Mg alloy is exposed to such an atmosphere A1203, MgAl204, or MgO. The specific... 

Prior to the introduction of Cu electroplating, the primary method used to form a multilevel structure of interconnections in integrated circuit applications was A1 and Al-alloy metallization.49 Localized porous-type anodization was developed in the 1970s to obtain planar interconnection metallization for multilevel large-scale integration (LSI) 26,46,50 For example, Schwartz and Platter showed that the subtractive etching for A1 interconnects could be substituted... 

Figure 12. Schematic of two-level interconnection metallization formed by anodic processing. Reproduced from Ref.26 with permission from ECS - The Electrochemical Society.

As device features diminish in size, Cu CMP has become the dominant CMP process for processing this device in the back end. Cu has several attributes that make it attractive as an interconnect material for such devices.f Electrochemically, Cu is noble compared to W and Al. Its hardness falls between W and A1 and will not scratch as easily as Al. It has higher electromigration resistance than W or Al/Cu, which has been conventionally used as the interconnect metal in current devices. 

A second critical requirement in interconnect metallization is the ability to fill small, nanometer-scale, features (i.e., cavities) rapidly and reliably. Unlike the current distribution on the macroscopic (wafer) scale which is typically controlled by the electric field (and therefore strongly affected by the conductivity), the current distribution on the... 

Copper is rapidly emerging as the interconnect metal of choice for the next generation of sub-0.25pm devices. It has superior mechanical properties, lower resistivity and higher electromigration resistance when compared to aluminum. Electrochemical deposition (electroless/electroplating) of copper is a versatile, inexpensive and reliable way of filling... 

The object of semiconductor lithography is to transfer patterns of ICs drawn on the mask or reticle to the semiconductor wafer substrate. The transfer is carried out by projecting the image of the reticle with the aid of appropriate optical elements of an exposure tool onto a radiation-sensitive resist material coated on the semiconductor wafer, typically made of silicon, and stepping the imaging field across the entire wafer to complete a layer. The shape of the IC pattern transferred to the wafer substrate is dependent entirely on the wafer layer being patterned. Examples of patterns include gates, isolation trenches, contacts, metal interconnects, and vias to interconnect metal layers. An advanced CMOS (complementary... 

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