High Density Interconnect Dielectric material

IPC-4104 This standard identifies materials used for high-density interconnection structures. A series of specifications (slash sheets) are defined for specific available materials. Each sheet outlines engineering and performance data for materials used to fabricate high-density interconnecting structures. These materials include dielectric insulator, conductor, and dielectric/conductor combinations. The slash sheets are provided with letters and numbers for identification purposes. For example, if a user wishes to order from a vendor and reference the specification sheet number 1, the number 1 would be substituted for the S ... 

The ILD CMP process has been used to polish plasma-enhanced tetraethylortho-silicate (PETEOS) or high-density plasma chemical vapor deposition (HDPCVD) film on deposited silicon wafer. Figure 15.2 shows the ILD CMP process. The stacking of additional layers on top of one another produces a more and more rugged topography. Between each layer, the dielectric is deposited as an insulating material. To obtain a multilevel interconnection, the surface of the wafer must be... 

Excellent, isotropic electrical properties. Dielectric constants of 2.4 to 2.6 have been demonstrated. Low dielectric constant is crucial as interconnect density increases. As space between conducting lines shrinks, inductance and cross-talk become problematic, but can be mitigated with lower dielectric constant materials. Polyimides, which are used extensively in the industry, exhibit anisotropic electrical properties in-plane dielectric constant can be as high as 4 while out of plane dielectric constant is generally above 3. 

It has been determined that Si02 needs to be replaced with a physically thicker layer of oxides of a higher dielectric constant (K) material, or high K gate oxides [1-8]. The maximum current density in interconnects between transistors resulted in the replacement of aluminum with copper as the conductor. The FET gate stack, which is the gate electrode and the dielectric layer between the gate and the silicon channel, is now the most serious problem. 

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