Gate stack

Chemical analysis of etching residues in metal gate stack for CMOS process... 

Fig. 2. SEM images of TaN gate stack with photoresist masks after etching (a) in pure CI2 and (b) CI2/O2. The experiments were performed at a pressure of lOmTorr, source power of 400W, and bias voltage of -200V.

More Cl and O were observed by adding 1% O2 in CI2 and the amounts of residues were removed by wet cleaning process. It is expected that the residues generated during etching on the gate stack can be removed by wet cleaning process such as dilute HF. 

Fig. 3. SEM images of (a) TaN, (b) TiN and (c) HfN gate stack with Si02 mask after etching in CI2. The experiments were performed in the same condition as in fig. 1.

Fig. 4. (a) TEM image of TaN metal electrode gate stack after Ch etching, revealing thick residues formation on the sidewall (etching was done in DPS) SEM image of TaN metal electrode (b) before and (c) after DHF cleaning. 

Fig. 6. AFM images of etched surface of HfN films after 1% DHF dipping with the time (a) 5 s, (b) 15 s, (c) 40 s (d) SEM image of metal gate stack after etching 5min in 1% DFDF, showing HfN film is laterally etched.

Why is Ti02 used in dye-sensitized solar cells (DSCs) What other oxides would possibly be useful As discussed in this Chapter, next-generation CMOS ICs will employ high-K dielectric films as the gate insulator. A potential roadblock to this replacement is the possible incompatibility with current gate stacks - explain this problem, with possible solutions. 

Dielectric breakdown in nanosize gate stack of state-of-the-art Si nanoelectronic devices has been one of the key reliability concerns. We present the recent development in using physical analysis techniques to decode the nature of the breakdown path or more commonly called as percolation path in ultrathin SiON and HfOi-based gate materials. 

Our strategy is to employ state-of-the-art transmission electron microscopy (TEM) which is capable of providing both spatial and energy resolution to study the distribution of oxygen deficiency in a BD path and understand its role in the oxide degradation process. Two examples will be illustrated for a 22 A SiON gate dielectric and a HfDa/SiOx based gate stack. 

Fig. 6a shows an example of a nanoscale breakdown driven thermochemical reaction induced microstructural defect in a poly-Si/Hft)2/SiOx gate stack... 

Similar to the results shown in Figs. 4 and 5, STEM/EELS analysis is in progress to study the nature and chemistry of the breakdown path in advanced high-k based gate stacks. 

Graphene field-effect transistors with a parylene back gate and an exposed graphene top surface have been reported [40]. A back gate stack of 168 nm parylene on 94 nm thermal silicon oxide permitted an optical reflection microscopy technique to be used for the identification of exfoliated graphene flakes. At room... 

It has been determined that Si02 needs to be replaced with a physically thicker layer of oxides of a higher dielectric constant (K) material, or high K gate oxides [1-8]. The maximum current density in interconnects between transistors resulted in the replacement of aluminum with copper as the conductor. The FET gate stack, which is the gate electrode and the dielectric layer between the gate and the silicon channel, is now the most serious problem. 

M. MacKenzie, A.J. Craven, D.W. McComb, S. De Gendt, Interfacial reactions in a Hf02/ TiN/poly-Si gate stack. Appl. Phys. Lett. 88(19), 192112 (2006)... 

Therefore, it ean be clearly observed that the existence of the low-k layer will increase the equivalent oxide thickness of the gate stack. The low-k layer should be as thin as possible to achieve the equivalent oxide thickness required by the International Technology Roadmap... 

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