HETA technique

Table 4.10 Original and modified architecture characteristics for HETA technique synthesized in 0.18 p CMOS process technology 61...

Table 6.5 Classification of the total 75,619 faults in the miniMIPS protected by HETA technique with VAR and BRA 73...

Original unhardened HETA technique Combined techniques... 

In order to perform the experiments presented in this Chapter, we implemented the miniMIPS hardened with the novel hybrid HETA technique and the software-based techniques Variables and Inverted Branches on both flash-based and SRAM-based FPGAs. We visited three facilities, used two types of energetio particles, and performed tests for SEE and TID. In the following, each radiation experiment and its results are diseussed in detail. 

Mendum, T. A., Sockett, R. E., andHirsch, P. R. (1999). Use of molecular and isotopic techniques to monitor the response of autotrophic ammonia-oxidizing populations of the heta subdivision of the class Proteobacteria in arable soils to nitrogen fertilizer. Appl. Environ. Microbiol. 65, 4155—4162. 

In the following sections, we will present the HPCT tool to automatically transform program codes into hardened ones, two known software-based techniques, called Variables and Inverted Branches, and three novel hybrid techniques to detect transient faults in embedded processors, named PODER, OCFCM, and HETA, combined with the previous known software-based techniques. 

Hybrid Error-detection Technique using Assertions (HETA) is the third and final hybrid technique presented in this book. It was initially based in the CEDA software-based technique and its abiUty to efiSciently detect control flow errors between different BBs, and PODER and its ability to detect control flow errors inside the same BB. HETA is aimed at both FPGAs and ASICs, since it implements a non-intrasive hardware module combined with transformation rules on the program code. 

Like PODER, HETA combines hardware- software-based techniques into a hybrid technique. Its main objective is to protect the system against control flow errors, which comprises (1) incorrect jumps to the begimiing of a BB, (2) incorrect jumps inside the same BB, (3) incorrect jumps to unused memory addresses, and (4) control-flow loops. It is important to note that HETA, just like PODER and OCFCM, cannot detect errors in branch instructions, where the execution flow graph... 

In the next subsections, the terminology used for HETA is presented, as well as the hardware-based and software-based sides of the technique. 

It is important to note that HETA, like PODER and OCFCM, cannot detect incorrect but legal jumps (according to the program graph). In order to do that, the Inverted Branches software-based technique, described in Sect. 4.3 is required. Also, HETA may present aliasing, when the program code has many BBs. With big apphcations, some signatures may start to repeat themselves and an error may not be detected by the technique. 

Like PODER and OCFCM, HETA can also detect control flow loops (4). In order to detect this kind of error, a watchdog timer is implemented. The counter is reset every time the software-based technique side enters a BB, by performing a Reset XOR instruction. When the counter overflows, an error is flagged. By doing so, the hardware module can detect a control flow loop that causes the execution flow to be stuck at a single instruction. 

HETA has to main drawbacks. The first one is the signature aliasing issue that may lead to undetected errors, when the protected application has a number of BBs bigger than possible signatures. The second one is that the technique requires access to the memory buses. Processors with on-chip embedded cache memories may not allow access of its memory buses to the hardware module. In such cases, another approach should be used. 

The implementation of HETA consists of the hardware module implementation and the software transformation. We have used the miniMlPS mieroproeessor as platform to implement the technique. The following subsections describe the implementations required to harden two case-study applications with HETA. 

One hardened program for each case study was generated using the HPCT and implementing HETA. Tables 4.8 and 4.9 show the overhead in execution time, code size, and data size for the matrix multiplication and bubble sort algorithms, respectively. They compare the original unhardened program with versions hardened by HETA and HETA combined with the Variables and Inverted Branches techniques (Combined Techniques). 

Such results show that software-based techniques combined with HETA can be used in harsh environments and allow designers to reach fast fault diagnosis and correction. When comparing to hardware-based techniques, such as Xilinx Triple Modular Redundancy (XTMR) with scmbbing, that require modifications to the microprocessor s hardware, we can notice an area reduction higher than 66% and still acceptable fault coverage of 96.9%. On the other hand, the hardened application takes 1.48 times the original time to execute and 6.5 % more area to implement the OCFCM hardware module. 

Detected faults errors detected by the software-based technique and HETA s hardware module that did not affect the matrix multiplication result ... 

Not detected errors errors not detected by the soflware-based technique and HETA s hardware module, but detected by the TMR. 

AZAMBUJA, J. ALTIERI, M. BECKER, J. KASTENSMIDT, F. HETA hybrid error-detection technique using assertions. IEEE Transactions On Nuclear Science, Los Alamitos, USA IEEE Computer Society, 2013. 

High-resolution NMR is a very powerful technique and can be used in a modified form (known as two-dimensional NMR) to establish the structures of proteins (see Chapter 23 on the accompanying website). Figure 21.8 shows the structure of a small protein known as LysM, which binds to bacterial cell walls. It is shown running from hlue at the nitrc en terminus, and it has an antiparallel heta sheet and three alpha helices. 

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