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Watchdog timer

Check watchdog timer alarm—often indicates hardware problem Operator turned controller off ... [Pg.1263]

Watchdog timer This is another valuable option for process control computers. It allows the computer to determine if the control program is being executed smoothly or if the program is hung up in a never-ending loop. In the second case an alarm alerts the operator that the computer has lost control of the process, due to software problems. [Pg.287]

Examples of these include watchdog timers and end-of-line monitors. [Pg.49]

Industrial process sector PE logic solvers have internally configured diagnostics. They are referred to as internal watchdog timers (IWDT) in this annex. IWDTs include software, hardware, and communication diagnostic subsystems provided by the manufacturer, within the PE logic solver. [Pg.89]

The limitations inherent in IWDTs may require the addition of external watchdog timers (EWDTs) for PE logic solvers performing safety instrumented functions. The use of EWDTs in no way eliminates the need for IWDTs for safety instrumented functions. [Pg.89]

The last kind of detection is the control flow loop (4). In order to detect this type of error, a watchdog timer is implemented. The counter is reset eveiy time the execution flow enters a BB, with the reset XOR instraction. When the counter overflows, an error is flagged. By doing so, the hardware module can detect a control flow loop that causes the execution flow to be stuck at a single instraction. [Pg.56]

NOTE 1 The watchdog confirms that the software system is operating correctly by the regular resetting of an external device (for example, hardware electronic watchdog timer) by an output device controlled by the software. [Pg.40]

For example, has a dynamic rather than a static mode of operation been adopted so that failures resulting in a stuck SIS output state can be detected, e.g., by watchdog timer ... [Pg.94]

Figure L.2 illustrates the relationship between lEC 61508 compliance and ANSI/ISA-84.00.01-2004-1 prior-use information, when examining alpha and beta testing, analysis, testing, and operating experience. As a minimum, an understanding of the unsafe failure modes (safe and dangerous) is required, so appropriate counter measures (e.g., watchdog timer, etc.) can be implemented. Figure L.2 illustrates the relationship between lEC 61508 compliance and ANSI/ISA-84.00.01-2004-1 prior-use information, when examining alpha and beta testing, analysis, testing, and operating experience. As a minimum, an understanding of the unsafe failure modes (safe and dangerous) is required, so appropriate counter measures (e.g., watchdog timer, etc.) can be implemented.
Implement diagnostics to detect the dangerous failure modes, e.g., watchdog timer (see ANSI/ISA-84.00.01-2004-2, Annex E). [Pg.197]

Using watchdog timers Using end-of-iine monitoring... [Pg.205]

Controller or control subsystem I/O card Operator—console Watchdog timer Power supply Other utilities Will operator know What should operator do Will the failure propagate to other machines/systems Any change needed for each of the items listed... [Pg.236]

Complementary to the hazard mitigating functions that are added in response to specific risks identified through the hazard analysis for the computer system, features such as watchdog timers, program sequence checking, reinitialization of variables and other fault detection mechanisms constitute good practice. Because of the need for simplicity of the system, these features are added only to the extent that they do not make the software unnecessarily more complex. [Pg.39]

As is customary in non-accessible embedded systems, UPMSat-2 incorporates a WatchDog Timer (WDT) to achieve fault recovery. That is a hardware timer that must be periodically recharged by software, otherwise it provokes a hardware reset. Taking into account the stability property of fixed-priority scheduling, the task that restarts the WDT has been assigned the lowest priority. Therefore, in case of an infinite loop in any task or transient overload, the WDT task will overrun its deadline and the on-board computer will be restarted. The hardware timer is programmed for a 15 s time interval and the WDT task has a period of 10 s. As a result, the deadhne of this task is 5 s. [Pg.95]

WatchDog Timer (WDT). The WDT can be clocked from the internal RC oscillator, the RTC oscillator, or the APB clock. [Pg.39]

PROFIsafe" Components of the safety critical communications systems addressing, watchdog timers, sequencing, signature, etc. [Pg.403]


See other pages where Watchdog timer is mentioned: [Pg.1260]    [Pg.1260]    [Pg.1261]    [Pg.388]    [Pg.388]    [Pg.297]    [Pg.333]    [Pg.942]    [Pg.203]    [Pg.12]    [Pg.246]    [Pg.147]    [Pg.170]    [Pg.372]    [Pg.200]    [Pg.28]    [Pg.140]    [Pg.26]   
See also in sourсe #XX -- [ Pg.554 ]




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