Drain-source current, calculation

Fig. 2.19. (a) Scheme of a transparent field effect transistor based on ZnO [191]. The gate electrode consists of tin-doped indium oxide (ITO) and the gate dielectric is a multilayer of AECE/TiCE (ATO). (b) Output characteristics (drain-source current as a function of the drain-source voltage) for different gate voltages. The saturation current is about 530 rA at a gate bias of 40 V. From this output characteristics a threshold voltage of 19 V and a field-effect mobility of 27 cm2 V-1 s-1 were calculated [192]... 

Figure 5.24 shows the layout of the FET structures used for mobility measurements. Field-effect mobilities /ipE can be calculated either from the saturation regime or from the linear regime of the drain-source current If s using the following equations [111] ... 

A polyacetylene field-effect transistor has been described622 but the response time is slow, apparently because the carrier mobility is low. An FET has been made from polythiophene but source-drain currents were less than 20 nA for drain voltages up to 50 V. The hole mobility was very low, calculated to be 2 x 10 5 cm2 V-1 s 1 623). 

As depicted in Figure 2.4.10(b), contact resistance at the source and drain electrodes results in a smaller than expected slope of the potential versus channel position profile. The profile is estimated by linear extrapolation between Vi and V2. Individual source and drain contact resistances are calculated by dividing the voltage drops AVs and AV by the source-drain current, respectively. By isolating the source and drain contact contributions to the total contact resistance, the gated four-probe technique provides more information than the transmission line technique, and it is possible to determine in one device (vs. several). An important caveat for the gated four-probe technique is that the extrapolated channel potential profile wiU only be valid for strict linear regime OFET operation (Vq V, ), where the channel potential profile can be expected to be linear and uniform. 

Figure 6A Schematic depiction of source and drain current versus drain potential when the source potential is fixed at a value much less than the formal potential of the redox cofactors calculated using Equation 6.9 (i.e., source-drain measurement) [6]. Lines labeled a-g indicate source and drain current for different drain potentials.

Figure 6.8 depicts and Ig plotted versus Eq for various values of V calculated on the basis of Equation 6.10, indicating that the maximum source-drain current for gate measurements occurs when Eq = E° and V is sufficiently large (>0.25 V at room temperature), yielding I = nFAk d /w. 

Figure 6.8 Schematic depiction of source and drain currents versus gate potential for different source-drain voltages calculated using Equation 6.10.

Here, G, conductance, characterizes the dependency of source-drain current on source-drain voltage for gate measurements when V is sufficiently small to yield a linear (ohmic) dependency. G specifically applies to the box geometry depicted in Figure 6.1. Figure 6.9 depicts /d and Is plotted versus V for various values of Eq calculated using Equation 6.10, where G is the slope of the line tangent to the curve when V < 0.05 V per Equation 6.14. The purpose of G is that it enables a standardized comparison of different materials of their ability to conduct... 

Figure 6.9 Schematic depiction of source and drain current versus source-drain voltage for indicated gate potentials calculated using Equation 6.10. For a given gate potential, the slope of the line tangent to current in the limit of small source-drain voltages is conductance for that gate potential based on Equation 6.15.

This differential equation can be solved for the boundary condition given in Eq. (1). With Eq. (3) the solution provides the possibility to calculate the total resistivity across the entire transistor channel and hence, the current between drain and source terminal 7d since 7d = Vd/7 tot-... 

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