Device technology node

The chemical component of CMP slurry creates porous unstable oxides or soluble surface complexes. The slurries are designed to have additives that initiate the above reactions. The mechanical component of the process removes the above-formed films by abrasion. In most planarization systems the mechanical component is the rate-limiting step. As soon as the formed porous film is removed, a new one is formed and planarization proceeds. Therefore, the removal rate is directly proportional to the applied pressure. To achieve practical copper removal rates, pressures greater than 3 psi are often required. These pressures should not create delamination, material deformation, or cracking on dense or relatively dense dielectrics used in silicon microfabrication on conventional dielectrics. However, the introduction of porous ultra-low-fc (low dielectric constant) materials will require a low downpressure (< 1 psi) polishing to maintain the structural integrity of the device [7-9]. It is expected that dielectrics with k value less than 2.4 will require a planarization process of 1 psi downpressure or less when they are introduced to production. It is expected that this process requirement will become even more important for the 45-nm technology node [10]. 

Water immersion ArF lithography was deployed for the first time in large-scale fabrication of critical layers of IC devices at the 45-nm technology node in 2008,... 

In addition, aspect ratio considerations, dependent on mechanical stability and pattern collapse propensity of resist lines, limit the thickness of resists designed for these technology nodes to ultrathin resist thickness regimes ( 100 nm and lower). However, the aspect ratio considerations must be balanced against the etch stability requirements that ensure successful pattern transfer to underlying substrates in a device. Both the aspect ratio and etch stability requirements must be balanced against the intrinsic resolution, particularly pitch resolution, of the resist in question. Hence, there is a trade-off between aspect ratio requirements and etch stability requirements on the one hand, and pitch resolution on the other. Therein lies the motivation for these advanced resist-processing schemes. 

The adoption of HM processes in IC device manufacture started around the 45-nm technology node they are expected to become the dominant resist process technology in technology nodes <32 nm because of their compatibility with double-patterning technology as well as for the reasons stated above. 

There has always been constant interest and effort in developing abrasive-ftee slurries for almost all the CMP apphcations due to their nonuse of abrasives and potentiality to eliminate any defects and scratches. Even though the defectivity from scratches was acceptable in older technology nodes, it will be detrimental to the device performance... 

Defects from CMP are the largest yield detractor for logic devices in advanced technology nodes. CMP defects such as polish residues, foreign materials, scratches, HM, and DE not only result in yield loss and reliability issues at the current interconnect level, but can also propagate upward and interfere with subsequent process steps to cause other types of defects at higher levels. 

B.H.J. Tseng, M.D. You, S.C. Hsin, Characterization and control of microcontamination for advanced technology nodes and 300-mm wafer processing overview and challenges, IEEE Trans. Device Mater. Reliab. 5 (4) (2005) 623—630. 

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