The VHDL design hierarchy

Any hardware design can be described in terms of its operation at different levels of abstraction, from system through to logic gate. At each level of this hierarchy the overall inputs and outputs remain the same but the functionality of distinct sections becomes clearer. When the local inputs and outputs and the function of a block are sufficiently defined, the hardware can be designed. The method chosen to achieve this implementation will depend on many factors and this topic is a whole book in itself  

VHDL is capable of describing a well-defined hardware block at any level of abstraction. A design entity is the VHDL representation of such a block and can be considered to be at ffie top of the design hierarchy. Within the design entity, the function of the hardware is often further decomposed by using external and internal blocks. 

External blocks are other design entities that have been previously compiled and stored in a library (section 3.4). These types of blocks are generally referred to as components. Each component can further extend the hierarchy by also using external and internal blocks to describe its own function. The present design entity can also be thought of as an external block. 

Internal blocks are self-contained functional units that have explicitly defined input and output signals. They therefore represent the next level down in the hierarchy. Again, an internal block may contain external or other internal blocks. The Block statement is used to create an internal block. 

The entity declaration is the interface between the external environment such as a top-level schematic and flie design. It is at the top of ttie design tree for every external block. Hence, it will usually contain a description of the inputs to and outputs from the block in the form of a port statement. An entity declaration without a port statement does not have any external connections. 

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A design entity contains an entity declaration and an architecture body. These are described in detail below. Figure 3.1 shows the organization of the VHDL design hierarchy and illustrates the main elements of an architecture body. The port connections, indicated by arrowheads, enable information to be passed between blocks and, at the top level, allow the design entity to communicate with the external environment. A design entity may contain any or all of the elements shown in the diagram. It will always have an entity declaration and architecture body at the top level. 

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