Concurrency signal assignment

For a combinational process, it has been shown in [12] how to eliminate the internal variables, and compute the transition function of all signals assigned in the process, as a set of concurrent signal assignments. In this section we will only illustrate a conditional form on a simple example in the two languages ... 

The translation produces one concurrent signal assignment for each node d the CIXGL For exanq>le, for operator OP with inputs INI and IN2 and output OUT, the following line of VHDL code will be generated ... 

Four architecture bodies have been constructed using concurrent signal assignments in the dataflow style. These are shown in Figure 4.3. 

Concurrent signal assignment architecture DATAFLOWI ofMUX4TOI Is begin... 

Concurrent signal assignment with additional parentheses... 

Those that evaluated every condition sequentially but still did not verify that only one of them was TRUE. These circuits contained Component instantiations or Concurrent signal assignments. 

The keyword Unaffected can be used in certain concurrent signal assignment statements to ensure that there is no change in the value of a signal given a particular condition. In this respect it is similar to the Null statement in sequential statement sections. Its use therefore implies the existence of feedback around the combinational logic. In some circuits this coxild possibly lead to hazardous conditions and so it should be used with caution. 

The order of evaluation of concurrent signal assignment statements is not determined by their actual sequence in the architectural description. 

Any combinational logic associated with the design must be placed in a separate process or be implemented using concurrent signal assignment statements. 

The fully synchronous process triggers on a falling-edge clock signal. If the reset signal PC is not active, the new state of S is then determined within the Case statement. The new state of S is used to update the outputs Q and QBAR in concurrent signal assignment statements that precede the process. Remember that the order of concurrent statements is irrelevant to their order of execution. 

The architecture BAD2 takes QBAR out of die process, ensuring that only one flip flop is inferred. However, in doing this, QBAR now becomes an unconditional concurrent signal assignment in which it is continuously assigned the inverted input D. Figure 5.33 illustrates tiiis circuit. The solution is to replace not D with not Q. ... 

No change to concurrent signal assignments or Decoder instantiaition ENABLER block... 

On synthesizing a mux structure using the concurrent selected signal assignment statements you find that one of the conditions of the primary inputs is not used (that is, left unconnected). Why ... 

DATAFLOW4 is an example of another concurrent statement, a selected signal assignment. This performs a similar function to die conditional sig-... 

The second architecture illustrates an alternative approach that uses an If-Else statement. This sequentially evaluates each expression in the construct tmtil it finds one diat is true and then executes the associated sequence of actions. This sequential statement is similar to the conditional signal assignment in that each possible two-way branch is evaluated in series, generating a multiplexer tree. Like the Case statement, the If-Else can initiate any number of actions within each brandv unlike its concurrent equivalent. 

Section 4.2 has illustrated a number of different ways in which a simple multiplexer can be designed in VHDL. Not all of these approaches are recommended for such a circuit, but die nature of the example has allowed a number of concurrent and sequential language statements to be introduced, not least various Signal assignment statements and the Case and If statements. For structural style architectures, a number of different techniques that allow components to be used in a design have also been demonstrated. 

A conditional signal assignment statement is similar to an If-Else statement. The former is executed concurrently and the latter sequential (inside a process). 

Signal assignments can be performed in a concurrent or a sequential manner. For the designer, the difference between these two methods is that... 

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