Wiring conductor pattern

This figure shows the conductor pattern 3 overlapping exposed parts of the electrode leads 13 and fanning out on the substrate 20 to form wider terminal areas for wire-bonding. Common connections 6 and 26 are provided. 

The electrical resistance R can be made in any arbitrary value. Owing to the processing equipment a value of about 1 kfl was chosen. The conductor pattern should have a much lower resistance, and is therefore made of gold. To keep the parasitic capacitance C low, and to avoid pinholes, the conductor pattern area is kept small. The terminals of the conductor pattern are connected to a print board by 20 pm dia. gold wires. Fig. 14 gives a schematic drawing of a thin film transducer. 

Additive In the additive process, formation of the conductor pattern is accomplished by adding copper to a bare (no copper foil) substrate in the pattern and places desired. This can be done by plating copper, screening conductive paste, or laying down insulating wire onto the substrate on the predetermined conductor paths. 

The gate layer (which is also typically used for some interconnect) is a conductor and is patterned both to establish interconnects and decrease the overlap capacitance with the source/drain layer which is a drag on performance in many applications. The gate layer is typically the best bonded to the substrate and is often also used to anchor layers that will be used for external connection (e.g. through heat seal connectors or wire bonding). The gate dielectric layer is typically patterned to allow interconnection between... 

This methodology for electronic pattern preparahon, where conductor line widths of 4-10 mil and dielectric via diameters of 6-10 mil are possible, has resulted in a new generation of sophishcated electronic devices. However, as with all electronic applicahons, the desire and need for additional miniaturization has necessitated the search for narrower conductor line widths and reduced via diameters. This quest is hindered by the limitahons of screen-prinhng technology. Clearly, the wire diameter and integrity of the screen limit the line widths and, especially, via diameters, which can be obtained using a thixotropic paste (Figure 7.1). 

With LTCCs, conductors are achieved by patterning conductive paste onto a ceramic green sheet by screen printing, then firing it simultaneously with the ceramic. The conductive material is one of the important constituent materials of LTCCs, and many characteristics are required of it so that it can meet a wide range of applications in high frequency components, wiring for substrates, and electrode terminals. 

Test Pattern. The basic conductor properties can be measured using a single test pattern, as illustrated in Fig. 8.15. These include resistivity, print definition and film thickness, film density, solder leach resistance, wettability, adhesion, and wire bondability. Each property will be discussed individually with reference to Fig. 8.15. Many applications require functional use tests which usually require specific test patterns and even multilayer construction processes. Similarly, numerous applications require standard conductor tests on thick-fihn dielectrics instead of the bare substrate. 

FIGURE 8.15 Conductor test pattern serving various fimctions (a) pads for adhesion, wettability, solder leach resistance, and wire bondability (p) serpentine pattern for measuring print thickness and resistivity and (c) pattern for print resolution. 

Adhesion. Adhesion measurements provide a figure of merit for the degree of conductor bonding to the substrate. The various mechanisms for bonding to the substrate are composition-dependent and were discussed in Sec. 8.2.3 under Inorganic Binders. This property is one of the most difficult to measure in terms of reproducibility and correlation. This is a result of the many factors that affect adhesion test results. These include, but are not limited to, the following specific conductor formulation, substrate, test pattern, test preparation, wire attachment method, solder type, and adhesion test method. 

Die (semiconductor) The conductor circuit pattern on the surface of a chip that is connected to a printed circuit board or chip carrier by wires (to a lead-frame) or solder bumps (Flip-chip bonding). 

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