Source/drain layer

For the sake of consistency, the four basic OFET layers will be referred to as the gate layer, gate dielectric layer, source/drain layer, and active layer. OFETs with integrated devices may also re-use one of these four layers for hybrid device integration or introduce additional layers for connectivity or other active device formation. The position of these layers is shown in two idealized OFET cross sections in Fig. 4.12. 

The gate layer (which is also typically used for some interconnect) is a conductor and is patterned both to establish interconnects and decrease the overlap capacitance with the source/drain layer which is a drag on performance in many applications. The gate layer is typically the best bonded to the substrate and is often also used to anchor layers that will be used for external connection (e.g. through heat seal connectors or wire bonding). The gate dielectric layer is typically patterned to allow interconnection between... 

Fig. 4.13. The process flow presented in [74]. Each layer is patterned using a shadow mask, except for the surface passivation layer which is blanket deposited. The surface passivation layer does not introduce any significant resistance between the gate and source/drain layer. The gate dielectric layer is only deposited where necessary due to the nature of the shadow mask geometry.

Fig. 4.15. The process flow described in [57]. The gate, gate dielectric, and source/drain layers are photolithographically patterned. The gate dielectric is passivated using octadecyltrichlorosilane, and the semicondnctor is deposited. A chromate sensitized aqueous polyvinyl alcohol based photoresist is then used to pattern the semiconductor. Uncrosslinked resist is developed with water and the exposed pentacene is etched using an oxygen plasma.

After stripping and cleaning of the source/drain layer, the semiconductor can be deposited. Purified pentacene can be evaporated on the prepared substrate directly. The exact optimal deposition conditions depend on a number of factors including the system configuration and the systematic errors in temperature and rate metrology due to geometrical factors, etc. As a starting point the substrate should be held at 60°C and the rate should be O.Olnm/s. 

For contact masks, a large variety of alignment marks are in use. One suggestion is shown in Fig. C.4. The marks should be large enough for the equipment of interest, and the gap between the box in square and cross in squares should be on the order of a. The four layers shown in Fig. C.4 are the gate (unlabeled), the via layer (VTA), the source/drain layer (S/D), and the semiconductor layer (ACT). 

An important consideration for testing is the quality of the bond between the metal layers and the substrate. The source/drain layer especially is susceptible to scratching (if probes are used) or delamination (if wirebonding, anisotropic adhesives, or heatseal connectors are used). This is an issue for circuits at nodes which will be externally bonded or probed. 

At least one of the metal layers needs to be scratch/peel resistant, and this is usually the gate layer against the substrate, although other combinations are possible (e.g. source/drain layer can also bond well to the gate dielectric and be deposited over a via). A t3rpical solution is to place a via in the center... 

Fig. C.8. (a) A typical test transistor, (b) a detail showing the overlap between the active area, gate, and source/drain. The large contact pads at the source, drain, and gate have large vias and metal from both metal layers. This significantly improves the reliability of contacts made using probing systems when the gate is more scratch-resistant than the source/drain layer on the gate dielectric.

While it is possible to measure the gate dielectric capacitance through QSCV overlap, it is advisable to include several metal/insulator/metal capacitors to allow independent measurement of the gate dielectric. The capacitors can be formed using the gate and the source/drain layers. 

Step 9. Si02 is blanket deposited over the substrate. The resist (mask 3) that has openings over the Si02 is deposited and patterned. The exposed Si02 is etched down to the source, drain, and gate layers, creating contact windows for metallisation. 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

Conventional electronic devices are made on silicon wafers. The fabrication of a silicon MISFET starts with the diffusion (or implantation) of the source and drain, followed by the growing of the insulating layer, usually thermally grown silicon oxide, and ends with the deposition of the metal electrodes. In TFTs, the semiconductor is not a bulk material, but a thin film, so that the device presents an inverted architecture. It is built on an appropriate substrate and the deposition of the semiconductor constitutes the last step of the process. TFT structures can be divided into two families (Fig. 14-12). In coplanar devices, all layers are on the same side of the semiconductor. Conversely, in staggered structures gate and source-drain stand on opposing sides of the semiconductor layer. 

In a MESFET, a Schottky gate contact is used to modulate the source-drain current. As shown in Figure 14-6b, in an //-channel MESFET, two n+ source and drain regions are connected to an //-type channel. The width of the depletion layer, and hence that of the channel, is modulated by the voltage applied to the Schottky gate. In a normally off device (Fig. 14-9 a), the channel is totally depleted at zero gate bias, whereas it is only partially depleted in a normally on device (Fig. 14-9 b). 

The thickness of the active layer is about 100-300 nm, while the source-drain distance (channel length) amounts to a few micrometers. The channel length is determined by the current requirements and usually exceeds 10 /xm. Other manufacturing schemes as well as alternative stmctures are described elsewhere [619, 621]. Technology developments for the next generation TFTs that are to be used for high-resolution displays have been summarized by Katayama [627]. 

Thin-fihn transistors have been fabricated by depositing 50 nm of CdS onto SiOz-covered n Si and evaporating two A1 elechodes (source and drain) onto the CdS [45]. Similar devices were also made using CdS deposited on polyimide substrates with three (source, drain, and gate) evaporated metal electrodes and various sputtered insulator layers for the gate electrode. 

III), were prepared by Kim et al. (4) and used in gate electrode, a gate insulating layer, an organic semiconductor layer, and in source/drain electrodes applications. 

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