Wire-load models

Physical synthesis tools read a circuit that satisfies timing constraints assuming optimistic timing estimates, based on zero wire load models. The first step is to... 

Area constraints are specified using the set max area command. The total area of a design is the sum of the area of all the cells used in the design and the area due to wires (if specified in the wire load model). 

Wire Loading Model Mode top Startpoint a (input port clocked by elk)... 

You are performing trial compile runs. You do not wish that wire loads be considered in these trial runs. Can one prevent DC from selecting a wirejoad model for a design, or does it default to a particular wire load model ... 

The different mechanisms of selecting the wire load model in DC is described in chapter 6. However, to prevent the use of any wire-load model, one must perform the following steps. Set the variable auto wireJoad selection to false. Also, if the ASIC vendor library has the attribute default wireJoad set to a particular wirejoad model, the following command must be used to remove the default.wirejoad attribute ... 

The set load -fanout number specifies the number of cells the output port of the design is driving. This information is used to calculate the net load from the wire-load model specified. 

Back-annotate physical information from placement in the Floorplan Manager. Create custom wire-load models for your design based on the back-annotated data. This wire-load can be based on physical grouping performed during step 2. 

Example 6.4 shows net resistance and net parasitic file written out from a commercial Florrplanning tool. In other words, the tool provides estimated resistance and capacitance values for each net in the design. This information can be back-annotated to DC to generate new more accurate wire load models as discussed in section 6.4 or to perform in place optimization. 

Used to create custom wire-load models after back-aimotation of estimated loads. 

Creating Wire Load Models After Back-Annotation... 

The designer explicitly specifies the desired wire load model. 

The set joad script specifies the load on every net in the design. Most floorplanning and place and route tools are capable of generating this information. The create wire load command be used with the -hierarchy option to generate wire load models for each sub-block in the design. 

Example 6.5 shows a custom wire-load model generated from Compass Design Automation s floorplan tool. This custom wire load model can be included in your technology library using the update lib command and then selected appropriately using the sct wire load command. These estimated wire-loads are not as accurate as... 

You are doing post-route static timing analysis using SDF file generated from layout tools. Do wire load models affect the timing after back-annotation You get different results for different wire load models. 

If the tool that generated the SDF file lumped the transition delay in with the net delay rather than the cell delay (DC assumes that the transition time is by default included in the cell delay), and if you have not back annotated your capacitance information as well, then when DesignTime tries to subtract the transition delay from the net delay it must base the calculations of transition delay on the wire load model. Wl-r vou read the back annotated timing, you should set the two variables if the trans time has been included in the net delay. 

If you set the above variables, DC calculates the transition delay and ts it from the net delay and adds it to the cell delay. It uses the back annotated v. jtances to calculate the transition delay. However, if you don t back annotate your capacitances, DC must use the capacitances in the wire load model. This might explain the differences you saw with different wire load models after back annotating the timing. 

You are writing out an SDF file from Design Compiler and do not get any INTERCONNECT delay being written out even thou you have specified the wire-load models. 

The INTERCONNECT delay consists of the Connect Delay component and maybe the Load Delay. When writing out SDF file from DC, you can specify whether the Load Delay should be included in the lOPATH delay or INTERCONNECT by using the appropriate options with the write timing command. Also if the resistance value in the wire-load model selected is 0, the Connect Delay component shall be 0. Here is an example. 

When back annotating values into Synopsys, the wire load model is taken into account. If the values written out from the initial design also contain the WLM, is there a way to specify no wire-load model in DC ... 

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