Wafer fabrication etching

The whole system is constructed from two silicon wafers, fabricated using photoresist by deep reactive ion etching (DRIB) [21]. The wafers were thermally bonded. Thereafter, inlet and outlet ports were machined and the single reactors isolated by DRIB. 

Figure 3.2 Schematic of the fabrication sequence used to etch the silicon structure of the ESI Chip using a double-side polished silicon wafer. (A) The wafer after completion of photolithography and RIE of the silicon oxide on sides one and two. (B) The wafer after etching of the inlet structure on side two (bottom side on the figure). (C) The wafer after spinning resist on side one (top side on the figure), photolithography and development to define the through-channel structure. (D) The wafer after DRIE of the through-channel structure to the inlet structure. (E) The wafer after DRIE of the annular space to define the nozzle. (F) The wafer after removal of the resist and silicon oxide from the wafer.

Silicon wafer test coupons were designed and fabricated by Case Western Reserve University using 51mm diameter silicon wafers. The wafers were etched with trenches in the size range of 0.5 to 10pm and then covered with an oxide layer. The wafer was diced into three 19 mm x 19 mm square devices. Each trench consisted of a 9 x 9 array of cells. The arrays were located at the center of the 6.35 mm x 6.35 mm active area in the center of each 19 mm square device. Each trench in Device 1 was 5 pm long, 1 pm wide, and 3 pm deep. Device 2 had dimensions 2x that of Device 1, and Device 3 had dimensions 4x that of Device 1. Finally a conductive seed layer of 200 A /1000 A Ti/Cu or Cr/Cu was sputtered on the chip surface. 

Gracias s group utilized a dry etch technique for the fabrication of conical nanopores in Si substrates." They dispersed gold nanoparticles (GNPs) on the surface of a single Si crystal wafer and etched GNPs containing Si wafers with CF4/O2 plasma. They obtained conical pores with a small pore diameter as small as 20 nm with this method. The enhancement of the etch rate in the vicinity of Au NPs was explained by... 

Fig. 7.13 Polymer cantilever fabrication process, (a) Evaporation of 5/50/50 nm of Cr/Au/Cr as release layer on a Si wafer, (b) Patterning of 1.5- am-thick SU-8 for the cantilever, (c) Evaporation of 5/60 nm Ti/Au for the resistors and wires, (d) Electroplating approximately 5 pm of Ni for the contact pads, (e) Patterning 3.5-pm-thick SU-8 for encapsulation of the resistors, (f) Patterning 200-pm-thick SU-8 for the microfluidic channel, (g) Release of the chip from the wafer by etching the Cr layer [Reprinted with permission from Johansson et al. (2005). Copyright 2005 Elsevier]...

A Systematic Study and Characterization of Advanced Corrosion Resistance Materials and Their Applications for Plasma Etching Processes in Semiconductor Silicon Wafer Fabrication... 

The killer defects which are generated during metal etching processes fall on metal lines and cause the loss of production yield in wafer fabrication. The killer defects may either come from chamber materials or etch by-products [21, 22,23,25,27]. 

After the detail study through a thorough process qualification, the new boron carbide coated chamber wall is used to replace the previously anodized aluminum surface. The new ceramic material such as YAG or Y2O3 is used to replace original high purity alumina. This configuration was introduced to semiconductor wafer fabrication for evaluation. Excellent etch performance, enhanced defect and particle reduction, and 50 to 100 times chamber lifetime improvement are reported. The production yield of the wafer fabrication also improved about 7% in production at the customer site (see Fig.l9) [41]. The following data provide some of the information. The sequence of the data collection is as follows ... 

The revolutionary chamber materials study under high density plasma has opened a new scientific field in the characterization of materials. Meeting the comprehensive requirements of plasma etching tools in semiconductor wafer fabrication with the technology node shrinkage is not an easy task. The efforts and methodology developed through these studies have built up the foimdation in the advanced materials characterization, development and application. 

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