Etching wafer fabrication process

Etching. After a resist is patterned on a wafer, the exposed or unwanted substrate is removed by etching processes. Subsequentiy the resist is removed, leaving a desired pattern in a functional layer of the integrated circuit. Etching is performed to pattern a number of materials in the IC fabrication process, including blanket polysiHcon, metal layers, and oxide and nitride layers. The etch process for each material is different, and adapted to the material requirements of the substrate. 

In order to circumvent these shortcomings, a fabrication process based on macro PS as a sacrificial layer has been proposed [Le30]. The process sequence is shown in Fig. 10.25. First etch pits in the desired pore pattern are formed on the n-type silicon wafer surface by photolithography and subsequent alkaline etching. Then deep macropores are formed by electrochemical etching according to the... 

Schematic of the Si-nMEA fabrication process (a) sputter Au layer on double-side polished wafer (b) pattern Au layer with liftoff process (c) spincoat and cure a polyimide layer (d) perform the double-sided photolithography to pattern etch pits (e) etch Si in ICP-DRIE to form Au/Si electrode (f) dice the wafer into a single die (g) RIE etch the polyimide layer with a shadow mask to expose current collecting region (h) electroplate Pt black on Au layer (i) sandwich both electrodes with Nafion 112 in a hot-press bonder. (Reprinted from J. Yeom et al. Sensors Actuators B107 (2005) 882-891. With permission from Elsevier.)...

Fabrication process of the DMFC is shown in Fig. 5.2. The simple structure enables easy fabrication. Chip size of the fabricated DMFC is 20 mm x 25 mm. A (100)-sihcon wafer of 200 pm thickness is nsed as the snbstrate. 0.5 m silicon dioxide is formed thermally and patterned to form throngh-holes and channels, (a)-(b) The channels of the front side are etched by KOH from top side (c) and through-holes are etched by deep-RIE from the backside (d). The width of the channel and the distance between two channels are 100 pm. A sihcon dioxide layer is grown thermally on the entire exposed snrface of the sihcon wafer for the isolation layer (e). 

Figure 5.9 Novel fabrication process for the second generation of micromachined electrospray emitter tips silicon support wafer (blue), 200 nm thick nickel etch-release layer (white) which is patterned using a HN03-based wet etch, negative photoresist SU-8 which forms the micro-nib support layer and tip which hosts the capillary slot (gold) and single photolithographic masking layer which defines the reservoir and tip (black).

A possible procedure for synthetic jet fabrication has been shown in Fig. 3. The first step in the fabrication process is the wet etching of the silicon wafer using KOH to form a cavity. The cavity is filled with electroplated nickel in the second step. A polyimide membrane is deposited over the silicon wafer using spin coating in the third step. The back side of the silicon substrate is etched using KOH to obtain the orifice hole. The orifice hole extends till the filled nickel inside the cavity and the nickel material are also etched away. The piezo-ceramic material is deposited on top of the membrane for actuation. In case of electrostatic-based actuation, aluminum electrode is deposited on the membrane. 

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