Up-down presetable counter

This section presents a more practical design example, employing some of the language constructs and features illustrated in this chapter. A behav-iotural design style has been adopted for this circuit, an up-down counter with a parallel loading facility. The counter is only 3 bits wide so that its characteristics can be observed without the needless repetition of logic. 

Every synthesis tool vendor will undoubtedly supply the same or very similar functions and so their use here is justified. It also enables the subject of opera r and function overloading to be introduced by an example before it is discussed in detail in the next chapter. 

The identifiers given in the Use clauses are all item specific. Hence, only the two required operator functions in the BIT ARITH package and the clock function in the BIT UTILS package are visible. 

LOADVAL in BIT VEC70R(2 downto 0) CK, CUCD, ENABLE, LOAD in BIT  

TEMPCOUNT = COUNTVAU - initialize the variable if LOAD= 0 then - parallel load the counter TEMPCOUNT = LOADVAU elsif ENABLE= 0 then - counter is enabled 

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Figure 5.27 Libraries, packages and entity of the up-down presetable counter.

Here is an example of an up-down counter with asynchronous preset and clear. 

Here is a model for a parameterized N-bit binary up-down counter with synchronous preset and preclear controls. The counting is synchronized to the rising edge of a clock. 

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