Up-down counter

Here is a model of an up-down counter that shows flip-flops being modeled. 

Here is an example of an up-down counter with asynchronous preset and clear. 

Here is another example. This is a 3-bit up-down counter that shows how a pre-built D-type flip-flop is used along with its remaining behavior. The key statements that are necessary to be added are the module instantiation statements. With such a model, a synthesis system retains the prebuilt component in the synthesized design to achieve the desired result this is shown in the synthesized netlist. 

Here is a model for a parameterized N-bit binary up-down counter with synchronous preset and preclear controls. The counting is synchronized to the rising edge of a clock. 

The operation of the staircase ADC can be made continuous by replacing the simple counter by an up-down counter controlled by the comparator. If increases, the comparator output goes HI and the counter counts up and if v, decreases, the counter counts dowm. When the DAC output cro.sscs v,. the counter alternates betw een and N - 1. a range that is within 5LSB of i,. This type of ADC works well when v, varies only slowly relative to the coiiv ersion tinte or when a continuous readout is important. 

To be sure, the valve position changes in discrete steps, as does the output of the up-down counter. The steps are about 1 percent, and the valve will attempt to follow each pulse registered by the counter. But because most valves are incapable of following the pulse rate of the counter, which may be as high as 100 pulses/sec, delivery is reasonably smooth. 

Mathematically, the up-down counter totals up the difference between the demand and the measured rates, appropriately scaled ... 

This section presents a more practical design example, employing some of the language constructs and features illustrated in this chapter. A behav-iotural design style has been adopted for this circuit, an up-down counter with a parallel loading facility. The counter is only 3 bits wide so that its characteristics can be observed without the needless repetition of logic. 

Figure 5.29 Synthesized top-level circuit of the up-down counter s architecture, BEHAVIOUR...

Table 5.5 Logic synthesis statistics for the process blocks COUNTING and CARRY in the architecture BEHAVIOUR of the up-down counter.

Develop an up-down counter that can count up to 32. If the maximum number is reached a 1-bit output signal MAX is set high If the coimter reaches zero, the 1-bit output signal MIN is set high. In either case the counter will stop until the direction of the counter is changed. 

---