Control-flow-dominated

In addition, effort has been spent on formal verification itself, especially regarding timing issues for control-flow-dominated systems. A study of propositional temporal logic has shown its feasibility to verify correctness of sequential logic circuits, CMOS transistor circuits, and finite state machine diagrams against each other [16]. This work has been received with great interest in the worldwide research community, since verifications were done that previously seemed untractable. It has been applied in the context of performance-driven controller synthesis, as described in chapter 10. 

This chapter concentrates on methods suitable for control-flow-dominated applications. A flexible library of complex building blocks, including predefined I/O interfaces and memories, is targeted. Emphasis is placed on scheduling and allocation techniques tuned to this domain and on the interactive environment in which the tools are embedded. The demonstrator of this chapter is a complete telephone answering machine controller. 

As stated above, the compilation process starts with a behavioral specification given using a Vhdl subset. The specification consists of an entity/architecture pair, with the architecture limited to a single process statement. The Vhdl subset used is slightly different from that used by ProcVhdl in order to accommodate properties of control-flow-dominated circuits. The main difference is that some restrictions of ProcVhdl concerning loops, loop exit statements, and wait statements have been removed. 

Accesses to arrays and ports are automatically converted to functional unit calls. For example, suppose we have an FU named mm, described in Vhdl as an array (thus it is represented as a memory device in hardware, the array index being the address). Assignments to ram in the initial description would then be replaced by WRITE requests, and if ram was used as an operand in some operation, this would be replaced by a READ function. For our control-flow-dominated target domain, we have chosen to realize the memory access as implied by the Vhdl description. No memory-oriented loop optimizations, as addressed in chapter 7 and 8, are foreseen here. 

Amical uses a dynamic loop scheduling algorithm [13, 12]. This algorithm is adapted to control-flow-dominated designs written in Vhdl, and is a development of the path-based approach proposed by Camposano [2]. Essentially, the scheduler reads in a Vhdl description and produces a behavioral FSM in the form of a transition table. Each transition (macro-cycle) corresponds to the execution of a control step under a given condition. A macro-cycle may need several basic cycles (clock cycles) for its execution. The top left window in figure 4 shows the transition table composed of two states and five transitions. 

K. O Brien, M. Rahmouni, and A. A. Jerraya. A VHDL-based scheduling algorithm for control-flow dominated machines. 6th Inti High-Level Synthesis Workshop, Dana Point Resort CA, Nov 1992. 

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