Signal inferring sequential logic

The shift register example has demonstrated how If and Wait statement templates can be used to infer sequential logic in a VHDL description. The format of these templates is reasonably fixed and signals and variables within the sequential logic must adhere to certain guidelines. In particular, the effect of creating incomplete If statements was demonstrated as one serious pitfall that should be avoided. 

Assign the new value of ihe counter stored in the variable back to the signal. The signal therefore infers sequential logic as it is assigned inside a synchronous section. 

The sequential statements inside die If must assign a value to a signal or to a previously undefined variable for the synthesizer to infer a flip flop and hence create a registered output. Otherwise, purely combinational logic will be generated. 

Any sequential statements can be used in a function except a Signal assignment and a Wait This means that a function cannot infer a sequential block of logic. 

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