Mealy finite state machine

In a Mealy finite state machine, the output is dependent both on the machine state as well as on the inputs to the finite state machine. This is shown pictorially in Figure 3-8. Notice that in this case, outputs can change asynchronously with respect to clock. 

Here is an example of a Mealy finite state machine. Variable MealyState holds the machine state, while NextState is used to pass information from the combinational logic always statement to the sequential logic always statement. Input Reset asynchronously resets the state to STO. 

It is now common practice, for verification as well as for synthesis purposes, to take the deterministic Mealy finite state machine (FSM hereafter for short) as abstract model for clock-synchronized circuits described at the register transfer level. The model is based on the following hypotheses ... 

A finite state machine is a quintuple Q,T,6,qo F) with Q being a finite nonempty set of states, S the finite nonempty input alphabet, 6 the transition mapping, qo a start state, and F the set of accepting states. In terms of a logic circuit, we usually let the input symbols correspond to data bits on a number of input lines and the states correspond to the values contained in the registers. In hardware applications, it is customary to introduce two derived machine concepts, known as the Moore and Mealy type machines. A (deterministic) Moore machine is described by a six-tuple (Q, S,<5,/m, r, < ), where Init is a set of initial states, T the output alphabet, and (j> Q — T the output function. In a Mealy machine, outputs are associated with the edges in the state diagram so we have Q x E —F. We will call a machine incompletely specified if the 6 function is not fully defined over its domain of states and symbols. 

A finite state machine (FSM) consists of a current state (P) and a next state (N), iq>uts (I) and outputs (O). State Machines can be classified as Mealy or Moore machines depending on how the outputs are generated. 

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