Clocked scan cell

Figure 8.1 shows a multiplexed flip-flop scan cell. In this chapter, we discuss only the multiplexed flip-flop scan style. However, most of the test design rules discussed are also applicable to other scan styles. This scan style is supported by most ASIC vendors. For a multiplexed flip-flop scan style the scan ports required are the scan-iny scan-enabley and scan-out ports. The normal clock is used in the test mode in this scan style. 

When scan cells are linked to form a scan chain as shown in Figure 8.1, all the scan cells are controllable and observable. Since shifting of data into the scan chain is performed serially, it takes N clock cycles to shift an entire pattern into the scan chain, where N is the maximum length of the scan chain. Configurations with multiple scan chains are supported by most synthesis tools. 

Clock skew in the scan path could result in a scan pull-through or a diverging scan chain. In other words, during the scan shift phase, due to clock skew the same scan bit can be loaded into two successive scan cells. 

The set scan path command can be used to specify which scan chain the flops in a sub-design must be assigned to, depending on the clock skew on that branch. Further, this command can also be used to explicitly order scan cells within a scan chain. This command provides a means to arrange the scan-cells in the scan-chain in the order of reversed skew. 

Illegal path violations can cause a substantial decrease in fault coverage, since the violating scan-cells will not capture data, that is, they are scan controllable only. One approach to avoid this, is to place the clocks in different capture clock groups, such that they are not clocked in the same cycle in the capture mode. Clocks are placed in... 

By default, TC allocates all scan cells clocked by the same clock, to the same scan chain. Also, scan cells clocked by different edges of the clock are placed in different scan chains. Hence, if one has only one test clock in the testmode, because of multiplexing the functional clocks, TC will place all the scan cells in the same scan chain, by default. 

You are running DRC (check test) on the top level after integrating your ASIC. Finding that TC is inferring the a nchronous reset line as a clock and all the scan cells with asynchronous reset pins being classified as constant-logic black-box cells. 

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