Plastic dual in-line package

Over 95% of all the microcircuits made are packaged in plastic, usually a transfer moulded epoxy resin. Changes in packaging technology will occur away from the familiar PDIP (plastic dual-in-line package) to smaller SOT or chip carrier formats but plastics will continue to be the dominant packaging material for cost reasons. At the same time there is a need to improve the reliability of plastic encapsulated devices (PEDs) as they find further use in professional and certain military applications. 

Adhesives are also tailored to meet specific requirements of the packaging or assembly technology used (Table 5.9). Thus, the requirements for single-chip packaging in hermetically sealed ceramic packages such as CERDIPs will be somewhat different from those of plastic dual-in-line packages (PDIPs) and plastic-encapsulated microcircuits (PEMs). 

One of the most common and recognizable first level packages is the plastic dual in-line package (DIP) as shown in Figure 2. This package provides a convenient case example for further discussion of the polymers and polymer processing used in first level electronic packaging. 

With the conventional technology, ICs are mounted individually in plastic or ceramic single-chip packages (SCPs), such as dual-in-line packages (DIPs) or chip carriers, and the SCPs are interconnected on printed wiring boards (PWBs). The number of pins on SCPs has increased significantly, and line widths on PWBs, like IC feature sizes, have followed a historical downward trend (2). However, the basic SCP-on-PWB approach has remained predominant. 

The rise in temperatme of an IC encapsulated in plastic is primarily determined by the thermal conductivity of the leadframe material, and is generally about twice that of its hermetically packaged equivalent. Until recently, the leadframe material has been exclusively a nickel-iron alloy (Alloy 42), and for a 14 lead dual-in-line package the thermal resistance (i.e., rise in die temperature per unit power dissipated) is about 120°C/W. In order to cope with the increasing power dissipation of ICs, high copper content alloys (OLIN) have been introduced to reduce the thermal resistance by about 50%. 

Fig. 6.1. Cross-sections through the two basic forms of plastic package (a) dual-in-line (b) mini-pack or low cost chip carrier.

---