Parasitics gate resistance

Recently, Cree Research Inc. reported on the first p-channel 6H-SiC MOSFET [6]. The device structure and output characteristics are shown in FIGURES 8 and 9, respectively. The device current and transconductance are very small (76 pA mm 1 at 40 V of drain bias and 16 pS mm 1, respectively, for a 7 pm gate length device). The performance of this device was limited by a large parasitic series resistance. Nevertheless, even these preliminary results show the feasibility of SiC CMOS technology, capable of operating at elevated temperatures. 

This simplified model does not capture the behavior in deep subthreshold, changes in current in the saturation region, gate leakage, and parasitic series resistances. These parameters will be considered separately and need to be included in comprehensive device models. 

The source and drain should overlap the gate at least a. Too little overlap will lead to some devices having ungated channel segments, which introduces a large series resistance and is problematic. Too much overlap increases the parasitic capacitance without improving performance. 

On-chip interconnects present parasitic capacitance and resistance as loads to active circuits. Such parasitic loads had little impact on earlier ICs because the intrinsic gate delay dominated the total gate delay. 

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