Gate Delays

PSpice includes gate delays in its digital simulations. To illustrate gate delays, we will create a two-phase, nonoverlapping clock using gate delays. Wire the circuit below ... 

Since gate delays are on the order of nanoseconds, we will set the clock frequency to 10 MHz. We will run the simulation for 500 ns. Fill in the Time Domain (,Transient/ dialog box as shown ... 

The time resolution of time-tag reeording is limited by the resolution of the counter that delivers the event times. Extremely high time resolution can be obtained from a TDC (time-to-digital eonverter) ehip. These ehips are combinations of a counter and an interpolation eireuit based on gate delays (see Sect. 4.2.2, page 55). A multiscaler based on a TDC actually comes elose to a TDC-based TCSPC device working in the time-tag mode. 

A high resolution can also be obtained if two delay lines with slightly different gate delay are used, i.e. a Vernier principle is applied [146]. The principle is shown in Fig. 4.14. 

Fig. 4.15 Delay regulation loop in the reference structure of a Vernier TDC. The gate delay in the gates A1 to An is regulated so that a known delay, TO, between start and stop is cancelled at the end of the delay lines A and B. The obtained control voltage is applied also to the Vernier structure that measures the time between the input pulses...

The setup shown in Fig. 5.43, right, uses a time-resolved camera system for detection. The camera uses a gated [125, 149] or modulated [460, 496] image inten-sifier. The source is scanned across the sample, and for each source position a sequence of images is taken at various gate delays or at several phase angles. 

For the reasons pointed out in (Banishev et al., 2008a), the same laser fluorimeter has been optimized for measuring the nanosecond fluorescence decay (the kinetic mode of the fluorimeter operation). The curve represents the dependence of the number NnfW of fluorescence photons in the detector gate (with wide tg) on the gate delay time tad with respect to a laser pulse. For the model (la) an expression for kinetic curve can be written as ... 

HiU, C.A. Thomas, C.L.P., Programmable gate delayed ion mobihty spectrometry-mass spectrometry a study with low concentrations of dipropylene-glycol-monomethyl-ether in ditx. Analyst 2005, 130, 1155-1161. 

Fig. 6.89 Lifetime measurements with a gated boxcar system with successively increasing gate delay time...

Fig. 9.79 Oscillatory structure of the cosine Fourier transform with narrowed central maximum for increasing values of the gate delay time T = 0, r, and 2t. The peak intensity has been normalized...

Fig. 9.80 Comparison of calculated (a) and measured (b) line profiles of level-crossing signals under observation with different gate-delay times (in ns). The different curves have been renormalized to equal centered peak intensities [1306]...

It should he emphasized that line narrowing is only observed if the time development of the phase of the upper-state wave function can be measured. This is the case for all methods that utilize interference effects caused by the superposition of different spectral components of the fluorescence. Therefore, an interferometer with a spectral resolution better than the natural linewidth can be used, too. However, a narrowing of the observed fluorescence linewidth with increasing gate-delay time T is only observed if the gating device is placed between the interferometer and the detector it is not observed if the gate is placed between the emitting source and the interferometer [1303]. 

If Sa = redundant and Sb = normal, the first operand must be normalized by setting the upper n/2 bits to zero (needs two gate delays). A normal addition will be performed then. 

In waveform recovery mode the boxcar averager operates rather like a sampling device, with the gate delay being swept over a range of values while the output is recorded (the gate width should be sufficiently narrow to match the temporal variation in the waveform to be studied). The result is a point-by-point record of the input signal waveform. 

Fig. 6.1 Example of interconnect-driven cloning. The arrival times of F and F2 are 0. The required arrival times of and S2 are 5. For simplicity, this example uses gate delays of 0. a Origintil circuit, b New circuit after cloning leaving buffering intact, c New circuit after cloning considering buffering...

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