Multiplexed description

Microfabrication involves multiple photolithographic and etch steps, a silicon fusion bond and an anodic bond (see especially [12] for a detailed description, but also [11]). A time-multiplexed inductively coupled plasma etch process was used for making the micro channels. The microstructured plate is covered with a Pyrex wafer by anodic bonding. 

As noted previously, there was an American University campus newspaper story in 1921 that discussed the burial of 800,000 worth of explosives as well as multiplex gas. The District of Columbia always presumed that this was on the edge of the campus, as the article stated. Indeed, there have been three large burials found in this vicinity to date. However, nothing approaching the description in the campus newspaper has been found. 

Speed depends on the capacity of the transmission lines and the processing speed of the additional devices, such as modems, multiplexing tools, switches, and routers. (A short description of these devices is given in Section 4, together with more details about transmission line capacity.)... 

Figure 4.5 illustrates two wajrs of constructing the multiplexer circuit description using the behavioural design style. The entity associated with both architectures has been rededared and is also shown. For these examples, a BIT yECTOR type signal S, 2 bits wide, has been dedared for the... 

The entity declaration and architecture body of each component is shown in Figure 4.9. Again these descriptions are compiled and stored in the working library where the multiplexer architecture, STRUCTURAL2, can access them. Unlike STRUCTURAL , however, this architecture does not declare the components in its declarative part. Instead it uses a package declaration to store the component declarations. A Use clause is then required to... 

These constraints can be specified either in the input description or entered interactively by the designer. Note that they are not mandatory. For example, if the cycle time is not given, then the cycle time is by default equal to the critical combinational logic delay in the final logic-level implementation. The final implementation contains both data-path and control. The data-path is an interconnection of functional units, registers and multiplexers. 

Section 4.3.1 describes the correspondence between hardware functional u-nits and models in the behavioral description. Registers and multiplexer are described in Sections 4.3.2 and 4.3.3, respectively. 

Synthesis results. The ECC was synthesized and mapped to cells in LSI Logic s LCAIOK library. Two experiments were performed to illustrate the effect of resource sharing. In the first experiment, the hardware resources implementing PARITY.3 and PARITY-4 were assumed to have small area cost. This assumption corresponds to the actual implementation of these resources based on their HardwareC description, e.g. PARITY 3 is a three bit XOR and PARITY-4 is a four bit XOR. In the second experiment, the area cost for these resources was increased ten-fold to demonstrate the case where the area reduction due to sharing resources outweighs the area increase due to multiplexers and latching registers. Synthesis results of these experiments are summarized in Table 11.9. 

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