Multilevel resists planarization

The formulation of a single-layer resist that can meet beyond-state-of-the-art demands is an arduous task. To date, very few such materials have been advertized, and their field performance is yet to be proven. The difficulty lies in the fact that requirements of sensitivity, etch resistance, and planarization are mutually exclusive. For example, thinner resists capable of higher resolution sacrifice substrate etching protection and planarization. Consequently, the focus of lithographers lately has centered upon multilevel-resist processes that distribute desirable resist properties among several different organic and inorganic layers. 

The practice of multilevel resist technology has evolved rapidly since its introduction in 1973 (39) largely through resist materials innovation. The first applications of this technology involved use of DQN-type resists over poly(methyl methacrylate) (PMMA) as the planarizing layer. The pattern was... 

As mentioned in Chapter 1, the present state of CMP is the result of the semiconductor industry s needs to fabricate multilevel interconnections for increasingly complex, dense, and miniaturized devices and circuits. This need is related to improving the performance while adding more devices, functions, etc. to a circuit and chip. This chapter, therefore, discusses the impact of advanced metallization schemes on the performance and cost issues of the ICs. Our discussions start with the impact of reducing feature sizes on performance and the need of various schemes to counter the adverse effect of device shrinkage on the performance of interconnections. An impact of continued device shrinkage on circuit delay is discussed. Then the need of low resistivity metal, low dielectric constant ILD, and planarized surfaces is established leading to the discussion of CMP. Finally various planarization techniques are compared to show why CMP is the process that will satisfy the planarity requirements of the future. 

The processes of planarization is vital for the development of multilevel structures in VLSI circuits. To minimize interconnection resistance and conserve chip area, multilevel metallization schemes are being developed in which the interconnects run in three dimensions. Figure 5-4 shows a schematic of the multilevel metallization made possible by planarization. 

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