Multilevel resist process

The formulation of a single-layer resist that can meet beyond-state-of-the-art demands is an arduous task. To date, very few such materials have been advertized, and their field performance is yet to be proven. The difficulty lies in the fact that requirements of sensitivity, etch resistance, and planarization are mutually exclusive. For example, thinner resists capable of higher resolution sacrifice substrate etching protection and planarization. Consequently, the focus of lithographers lately has centered upon multilevel-resist processes that distribute desirable resist properties among several different organic and inorganic layers. 

X-ray lithography also takes advantage of the increased resist sensitivity due to the thinner imaging films of multilayer systems. Thinner imaging films further improve X-ray resolution by minimizing the penumbra effect, a problem associated with an uncollimated X-ray beam. Consequently, the oblique exposure of features near pattern edges are minimized by multilevel resist processes, thereby restoring the desired profile. 

The current technological competition for practical fabrication of 0.5 - 1.0 pm feature is in between photolithography and electron beam direct writing, and between single layer and multi-level resist. For less than 0.5 pm, the use of electron beam writing with multilevel resist will be inevitable. Further developments in electron resists from the standpoint of both resist chemistry and process development will be necessary to establish the electron beam lithography. 

Hardness as resistance of a material against penetration of another body marks a decisive material characteristic. The hardness of important construction materials can be influenced or selectively set by special hardening processes. Hardening is based upon different principles, e.g., the formation of martensite in steels as a result of thermal treatment For nonferrous metals, precipitatiOTi hardening plays an important role. Alloying elements are deposited by a multilevel thermal process. Their phase boundaries and size influence the increase of hardness and stability decisively. This attribute improvement is based upon the hindrance of the motion of dislocation (Bargel and Schulze 1988). 

The selective Cu deposition process was suggested by Ting and Paunovic (13) as an alternative means of fabricating multilevel Cu interconnections (Fig. 19.4). The first step in this through-mask deposition process (14) is the deposition of a Cu seed layer on a Si wafer, and then a resist mask is deposited and patterned to expose the underlying seed layers in vias and trenches. In the next step, Cu is deposited to fill the pattern. After the Cu deposition mask is removed, the surrounding seed layer is etched and dielectric is deposited. Electroless Cu deposition has been suggested for the blanket and selective deposition processes (15). 

Ion bombardment can be used to enhance resist etch rates and thus achieve anisotropic resist profiles. Reactive sites produced by bombardment permit more rapid attack by oxygen species in the plasma. Multilevel processing (181,182), in which an etch-resistant layer serves as a mask to pattern... 

As mentioned in Chapter 1, the present state of CMP is the result of the semiconductor industry s needs to fabricate multilevel interconnections for increasingly complex, dense, and miniaturized devices and circuits. This need is related to improving the performance while adding more devices, functions, etc. to a circuit and chip. This chapter, therefore, discusses the impact of advanced metallization schemes on the performance and cost issues of the ICs. Our discussions start with the impact of reducing feature sizes on performance and the need of various schemes to counter the adverse effect of device shrinkage on the performance of interconnections. An impact of continued device shrinkage on circuit delay is discussed. Then the need of low resistivity metal, low dielectric constant ILD, and planarized surfaces is established leading to the discussion of CMP. Finally various planarization techniques are compared to show why CMP is the process that will satisfy the planarity requirements of the future. 

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