Memory access

As noted above, one of the goals of NAMD 2 is to take advantage of clusters of symmetric multiprocessor workstations and other non-uniform memory access platforms. This can be achieved in the current design by allowing multiple compute objects to run concurrently on different processors via kernel-level threads. Because compute objects interact in a controlled manner with patches, access controls need only be applied to a small number of structures such as force and energy accumulators. A shared memory environment will therefore contribute almost no parallel overhead and generate communication equal to that of a single-processor node. 

Transputers. At higher levels of coimectedness there is a wide variety of parallel computers. A great many parallel computers have been built using INMOS Transputer chips. Individual Transputer chips mn at 2 MELOPS or greater. Transputer chips have four communication channels, so the chips can readily be intercoimected into a two-dimensional mesh network or into any other interconnection scheme where individual nodes are four-coimected. Most Transputer systems have been built as additions to existing host computers and are SIMD type. Each Transputer has a relatively small local memory as well as access to the host s memory through the interconnection network. Not surprisingly, problems that best utilize local memory tend to achieve better performance than those that make more frequent accesses to host memory. Systems that access fast local memory and slower shared memory are often referred to as NUMA, nonuniform memory access, architecture. 

The above entity dictionary module provides fast, in-memory access of most frequently accessed data for the compound registration process while keeping the in-memory cache up-to-date. In a multitiered system, controlling network traffic is critical to its speed and user experience. The above design eliminates the need of querying the database every time a piece of data is asked for, and since the system can use the cached dictionaries to display only the valid entities to the user, it also reduces human errors. 

It is possible to improve the performance of the hardware (hereafter called the MVP-9500) by providing interrupt facilities to signal completion of operation(s) or to request more data and also by moving data via direct memory access rather than under Z80 program control. These, and other refinements, were... 

The external memory access unit provides the interface between the AFP and the central, high-performance, random access memory store. Each external memory access unit can provide peak data I/O rates of 3.2 billion bits per second and sustained I/O rates of 800 million bits per second. Thus, the total sustained capability of an Advanced Flexible Processor from the two ring port I/O units and the two external memory access units is 3.2 billion bits per second. 

Centralized High Performance Memory. A multiprocessor system of AFPs may share a common, high-performance random access memory store (HPR) between processors. All system HPR requests sent from the external memory access units (XMAU) of the AFP s are managed by the Storage Access Controller (SAC). Multiple SAC s may be employed as memory requirements are expanded. Each SAC is capable of transferring data to and from the AFP array at a sustained rate of 6.4 billion bits per second. 

NUMA is one of the fundamental concepts needed to understand the design of a parallel software application. Every modern computer has several levels of memory, and parallel computers tend to have more levels than uniprocessors. Typical memory levels in a parallel computer include the processor registers, local cache memory, local main memory, and remote memory. If the parallel computer supports virtual memory, local and remote disk are added to this hierarchy. These levels vary in size, speed, and method of access. In this chapter, we will lump all these differences under the general term nonuniform memory access (NUMA). Note that this is a broader use of the term than is often found in computer science literature, where NUMA often refers only to differences in the speed with which given memory items can be accessed using the same method. In our use, memory access is often synonymous with data transfer. ... 

In designing a complex parallel program, it is useful to think of any parallel computer in terms of a NUMA model in which all memory, anywhere in the system, can be accessed by any processor as needed. One can then focus independently on the questions of memory access methods (which determine coding style for an application) and memory access costs (which ultimately determine program efficiency). 

The choice of memory access methods, which is determined by the programming model and tools, is subject to great variation. This topic is discussed in a later section that deals with models and tools. Typical memory access... 

Memory access costs are determined by the interaction between program structure and the performance characteristics of the computer system. Understanding these interactions at a high level of detail is typically complicated. However, a useful rough approximation of the memory access cost for a program can be obtained by modeling each transfer between memory levels as a fixed start-up cost (S) plus an incremental transfer cost per data unit (X). For example, the cost for a processor to fetch L data units at once from a remote memory into its local memory, cache, and registers can be modeled as follows ... 

It is impossible to derive a general model that applies to all application domains and all computer systems." In theory, one can predict performance from first principles, but this would require a detailed understanding of every part of the computation and how its memory access (data communication) patterns interact with the computer s hardware and operating system. Except for small computational kernels, it is not feasible to acquire such understanding. In practice, a more satisfactory approach is to construct a fairly high level model using approximate functional forms for the amount of computation, load balance, and overheads. 

NUMA Nonuniform memory access describing a configuration in which locations in memory may vary in the cost and mechanism of access. 

CPU olf-load mechanisms such as Direct Memory Access (DMA)... 

Interleaving memory banks mean that the memory is organized into B banks. Consecutive memory locations are stored in adjacent memory banks a word with address a is stored in bank number a mod B. The memory cycle time is the minimum time between accesses to a memory chip. This means that there is a maximum rate at which a memory chip can receive requests and consequently a minimum time between two accesses to the same memory bank, the bank busy time. This has performance implications for a program that has a memory access pattern that hits the same bank more often than the bank busy time. This is called... 

When the CPU requests a data item from main memory, the memory subsystem will check to see if it can be found in cache. If the data is not in cache, a cache miss occurs. When this happens the data item will be searched for at lower levels of the memory system and when it is eventually found it is brought into the cache. Data are fetched from memory in units of a cache line. This kind of memory organization is motivated by the observation that data that is used often should be accessible as quickly as possible and when a data is accessed it is also very likely that data items located close to it in memory will also be accessed soon. So memory access patterns which are local in space and time will be quickly serviced. Molecular Dynamics simulation algorithms often have a quite a lot of potential for memory access patterns that are local both in time and space. How well this can be exploited is very much dependent on the data-structures that are used in implementations. Which, of all possible data-structures, are optimal for MD is currently an open question. 

Another feature of the bus is that it allows devices to bypass the processor and write their information directly into main memory. This feature is known as direct memory access, or DMA. Each type of bus has a different number of channels that can be used for DMA. If two devices are set to the same DMA channel, neither device will write information to memory correctly thus, neither device will work. 

In general, there are four main types of PC resources that you might need to be aware of when installing a new component interrupt request (IRQ) lines, memory addresses, direct memory access (DMA), and I/O addresses. 

Direct memory access (DMA) is a method used by peripherals to place data in memory without utilizing (or bothering) the CPU. As an example, a sound card can buffer music in memory while the CPU is busy recalculating a spreadsheet. The DMA peripheral has its own processor to move the data. It uses dead time on the ISA bus to perform the transfer. At the hardware level, DMA is quite complex, but the important feature to remember is that the transfer of data is accomplished without intervention from the CPU. 

DMA (direct memory access) A method of transferring information directly from a mass-storage device such as a hard disk or from an adapter card into memory (or vice versa), without the information passing through the processor. 

A. Direct Memory Access (DMA) channels allow a device to write directly to memory. Bus mastering allows devices to write directly to each other. See Chapter 5 for more information. 

It is important to realize that many of these considerations are not only important for GPU programming. The arrangement of data in a data-parallel fashion, for example, is also important for parallel programming of distributed memory architectures, which are found in most of today s standard CPU clusters. Thus many of the techniques employed to improve the parallel efficiency of quantum chemistry codes are also applicable to GPUs. The same holds for the optimization of memory access patterns. A general... 

PCI-interface The PCI-interface writes the data via direct memory access (DMA) into the PC-memory. The data transfer rate achieved is 85 MB/s which has to be compared with an expected data rate of 20 MB/s. 

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