Mask levels

Figure 8 is a plot showing the effect of the defect parameter x on yield for 1, 5 and 10 mask levels. Note how rapidly chip yield decreases as the number of mask levels (L) increases. 

MLR systems can be classified by the number of layers and the function of the PCM, e.g., two-layer RIE PCM. Some authors prefer to use "bi-level," "tri-level," "double-layer," "triple-layer," or any other permutation of these words to denote the number of layers. The word "layer" and simple numerical adjectives are used here, because "level" may cause confusion because of its association with masking levels and because simple numerical adjectives pronounce better when the number of layers exceeds three. 

The next step in the threshold estimation is the calculation of the just-masked noise level (also called masking level) in the cochlear domain using the tonality index and the convolved spectrum. This is done by first calculating the required signal to noise ratio SNRb for each threshold calculation band b. 

The design of the imager presented in US-A-5171994 eliminates previously used optical windows consisting of a conductive thin semi-transparent chromium layer. The elimination of the chromium optical window results in an increased pixel-to-pixel uniformity, fabrication with only four mask levels and an increase in wafer yield. The detector is claimed in this patent while the method of fabrication of the device is claimed in US-A-5130259. 

Fig. 11.4. Optical micrographs of patterned mask levels by digital lithography for (a) gate level, (b) island level, and (c) source/drain level.

Fig. 10.23 shows a cross-sectional view of a typical circuit for a scanner, and shows the p-i-n sensor and the pass transistor. This particular circuit takes nine mask levels. The metals used are chromium and aluminum, the former for contacts to the TFTs and sensors and the latter for the interconnecting lines. The transparent conducting contact to the sensor is made with ITO and polyimide is used for passivation and isolation of the devices. 

The second constraint is that on critical mask levels nearly monochromatic exposure will be required in order to obtain high quality images. The requisite reduction in photon flux will lead to camera throughputs in the neighborhood of 60 wafers per hour. Tight registration limitations may further limit this number but it will be used as a reasonable throughput upper limit for VLSI wafers in next four to five years. 

The LELE approach can in principle be applied to arbitrary patterns by appropriately splitting into mask levels. While the LELE approach has been demonstrated to work in production environments, it has the disadvantage of doubling the cost of patterning for the critical layers. Another limitation is the effect of overlay error on the space CDs overlay errors translate directly into CD errors, as shown in Figure 3.8. This places severe demands on the overlay accuracy of future exposure tools. Self-aligned spacers for double patterning could avoid this issue. ... 

The simplest structure is the photodiode, shown in Figure. This structure relies on just a single p-n junction and is easily realized in commercial CMOS processes. Double junction p-n photodiodes can also be created. Figure(a) shows the schematic of the cross-section of this type of photodetector, and a physical mask-level CAD layout of this is shown in Figure 10. Again, the light sensitive areas can be made to be any size, but the depth is not under the designer s control when a commercial CMOS process is used for fabrication. 

The SOIMUMPS process is based on bulk micromachining of a silicon on insulator (SOI) wafer using four mask levels. It was originally developed for the fabrication of MEMS variable optical attenuators (VOAs) based on the use of a thermal actuator to control an optical shutter [18]. A cross-sectional diagram of an SOI wafer is shown in Figure 1.12. 

The process uses four mask levels (PAD METAL, SOI, TRENCH, and BLANKET METAL) that are used to pattern fine metal features on the device layer, holes through the device layer, holes through the substrate, and shadow-masked metal features on the device and substrate layers. The process starts off with a 4 in. SOI wafer (substrate 1-10 Q-cm, n-type, device layer 110 Q-cm) that is heavily phosphorus doped at the surface (15 25 Q/n) by solid source diffusion from a PSG layer during a 1 h anneal at 1050°C in argon. The PSG is then stripped in a wet etch. 

In the upper part of Figure 1.18, the first oxide layer in the Poly MUMPS process has been patterned with the ANCHOR 1 mask level, with the etch stopping on the nitride layer on the left and on the PolyO later on the right. A polysilicon layer, Polyl, is then deposited and... 

Layout is the activity that is used to define the features on each mask level, and the relationship between features on different mask levels. There are a number of different computer-aided design (CAD) tools available for layout, with some being more user friendly than others. Some examples of layout editors include L-Edit, MEMS Pro, IntelliSense (IntelliMask), AutoCAD, Jale3D, and Coventor (Designer). Some layout editors come with process setup files for the available MPW processes, which can make layouts for these processes much simpler. Some layout tools also include the ability to do automated design rule... 

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