Optimization logic preservation

We extend RUMBLE to improve the locations of individual logic gates other than latches. Further, we show how to find the optimal locations of multiple gates (and latches) simultaneously, with additional objectives. Incremental placement of multiple cells requires additional care to preserve timing assumptions, optimizing... 

All three levels of optimization effort were attempted - low, medium and high. In the first instance, only the component is optimized (preserving the hierarchy) The statistics for each stage are detailed in Table 4.8. In this table the values have been doubled to account for two identical components. The component s final circuit, generated after a high level of effort, is shown in Figure 4.38. It would appear that all redundant logic has been removed and even the delay on the critical path has been reduced. The optimization process has more than halved the area of each component. 

As this example has two clearly distinct sections, one combinational and one sequential, the hierarchy has been preserved and each process optimized independently. Again only area optimization has been attempted to remove simply the redundant or duplicated logic. Low, medium and high levels of effort were employed. 

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