Gate level

As in the previous example, the flip-flops in the 74161 must be initialized at the start of the simulation. Select the Gate-level simulation Options as shown in the right screen capture below. We will run a Transient Analysis for 130 ms. Fill in the Time Domain (Transient) options as shown in the left screen capture below. 

In the previous section we used the Digital Setup to initialize all flip-flops to the zero state. Suppose that instead of clearing the flip-flops, we specify the initial states as unknown (X). We will be using the circuit shown on page 487. Follow the procedure for running the analysis, except fill in the Gate-level Simulation Options as shown below ... 

The Gate-level Simulation Options should be specified as X as shown below ... 

S0LUTI0I1 Wire the circuit as shown. A l kHz clock is used. Use the Gate-level Simulation Options dialog box to set all flip-flops to an initial state of 0. 

Fig. 11.4. Optical micrographs of patterned mask levels by digital lithography for (a) gate level, (b) island level, and (c) source/drain level.

Gate level primitives can be instantiated in a model using gate instantiation. The following gate level primitives are supported for synthesis. 

The term designer is referred to in many places in the text. It is used as a generic term to refer to any reader of this text. In addition, the term synthesis tool and synthesis system are used interchangeably in the text. Either of these refers to the program that reads in a Verilog RTL model and generates a gate level netlist. 

Having produced a gate level netlist, a logic optimizer reads in the netlist and optimizes the circuit for the user-specified area and timing constraints. These area and timing constraints may also be used by the module builder for appropriate selection or generation of RTL blocks. 

In this book, we assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are described in Appendix B. The module building and logic optimization phases are not described in this book. 

Figure 5.5.18 illustrates the ScL procedure used by Loo and coworkers to fabricate laminated pentacene TFTs. The top substrate, containing the [tCP-printed source and drain electrodes, was constructed on a PDMS-coated plastic substrate [89]. The bottom substrate was constructed on an ITO-coated plastic substrate. The ITO, patterned photo lithographically to define the gate level, was coated with an organosilesquioxane spin-on glass, which comprises the dielectric. Pentacene [44]... 

To optimize the gate level design, let us look at the performance of a single CMOS inverter as shown in Fig. 8.1. Delay of a gate is typically defined as the time difference between input transition and output transition at 50% of supply voltage. The inverter gate delay can be analytically expressed as... 

Gate level At this level, the characteristics of a system are described by logical links and their timing properties. 

From an experimental point of view, so as to remain in a linear domain, these applied stresses need to be low in amplitude (e.g. around 10% of the voltage or current). However, this amplitude needs to be significantly greater than the noise gate levels on the measuring device. 

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