Gate level netlist

The term designer is referred to in many places in the text. It is used as a generic term to refer to any reader of this text. In addition, the term synthesis tool and synthesis system are used interchangeably in the text. Either of these refers to the program that reads in a Verilog RTL model and generates a gate level netlist. 

Having produced a gate level netlist, a logic optimizer reads in the netlist and optimizes the circuit for the user-specified area and timing constraints. These area and timing constraints may also be used by the module builder for appropriate selection or generation of RTL blocks. 

At this point the design consists of two levels. One is the microarchitecture netlist, the other is a technology-specific gate-level netlist for each microarchitecture component. The micro architecture optimizer first employs rules that make transformations that should improve both time and area. For example, converting a register and incrementer into a counter. Next, the critical paths are identified and optimized. Once critical paths have been processed, the microarchitecture optimizer operates on non-critical components, making similar decisions as in the critical path improvement phase but this time with an eye toward area improvements. The microarchitecture optimizer then produces a VHDL netlist that is passed to the fioorplanner/layout assembler for layout. 

In this book, we assume that the target netlist is at the gate level. The logic gates used in the synthesized netlists are described in Appendix B. The module building and logic optimization phases are not described in this book. 

To perform gate level simulation of a VHDL netlist one requires the VHDL simulation libraries from the ASIC vendor. The Synopsys liban utility can generate the VHDL library models from the synthesis technology library. For tiie more complex cells, simulation models will have to be manually created. The VHDL models generated are encrypted so that the vendor proprietary information is protected. 

Convert the netlist of CLBs and lOBs to Xilinx primitive cells from the Xilinx primitive library. The Xilinx placement and route tools accept only a gate level description. To convert this netlist of CLBs and lOBs to a netlist of Xilinx... 

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