Gate metal deposition

Two different kinds of catalytic metal structure are required. Thick films, which are assumed to be dense, are needed for high-temperature operation and detection of excesss oxidizing or reducing molecules in environments such as exhaust gases. Porous metal films are needed for selective detection of molecules such as NHj, CO, NO, and HC in excess air in environments such as diesel exhausts or flue gases. 

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Figure 15. Simplified process sequence for the fabrication of an NMOS transistor (a) substrate preparation, (b) selective exposure of substrate, (c) mask formation by differential solubility, (d) etching, (e) stripping of resist, (/) doping, (g) reoxidation of silicon surface, (h) formation of gate oxide, and (i) metal deposition and patterning. Abbreviations are defined as follows p-Si, p-type silicon PR, photoresist S, source G, gate and D, drain.

The TFT fabrication process on glass substrates starts with 100 nm of Cr for the gate metal, and is followed by a PECVD 200 nm thick Si3N4 dielectric with a 30 nm thick SiC>2 surface layer. The source drain metal is Cr/Au. Each of these layers is patterned using printed wax masks and chemical etching, steps a to d in Fig. 11.8. The surface is modified with a solution deposition of a self-assembled monolayer of octyltrichlorosilane (OTS-8) before inkjet printing deposition of the semiconductor. It has been shown that the OTS-8 layer affects the structural order of PQT-12 in thin films, improving the performance of the TFT [23]. Encapsulation and possibly other subsequent layers may be needed on the TFT, but these are not discussed here. 

The metal-on-polymer interface has been the most studied Interface as metals can conveniently be deposited by evaporation in situ 1n a controllable fashion in a UHV system (26-33). In the case of polyimide, Cu and Cr have been the most studied metals but other metals including N1, Co, Al, Au, Ag, Ge, Ce, Cs, and Si have been studied. The best experimental arrangement includes a UHV system with a load lock Introduction chamber, a preparation chamber with evaporators, heating capabilities, etc., and a separate analysis chamber. All the chambers are separated by gate valves and the samples are transferred between chambers under vacuum. Alternative metal deposition sources such as organometall1c chemical vapor deposition are promising and such techniques possibly can lead to different interface formation than obtained by metal evaporation(34). 

Since the ISFET is based on the field-effect transistor, let us recall briefly how the latter operates (see, e.g.. Ref. 98). The field-effect transistor (Fig. 19a) represents the so-called MIS (metal-insulator-semiconductor) structure (hence the abbreviation MIS-FET), i.e., a semiconductor base, onto which an insulating layer and a metal electrode (gate) are deposited. The base usually is a p-type silicon plate and the insulator, a Si02 or Si3N4 layer. With a thickness of 100-200 nm, the resistance of this layer is of the order of 10 fl. Two regions are produced in the base by local... 

The high deposition temperature excluded the manufacturing of simple circuits using silicon nitride as gate dielectric for transistors with a metal gate electrode. Therefore, another gate dielectric, deposited at lower process temperatures, is necessary. 

Polysilicon. Polysihcon is used as the gate electrode material in MOS devices, as a conducting material for multilevel metallization, and as contact material for devices having shallow junctions. It is prepared by pyrolyzing silane, SiH, at 575—650°C in a low pressure reactor. The temperature of the process affects the properties of the final film. Higher process temperatures increase the deposition rate, but degrade the uniformity of the layer. Lower temperatures may improve the uniformity, but reduce the throughput to an impractical level. 

Fig. 9. Fabrication sequence for an oxide-isolated -weU CMOS process, where is boron and X is arsenic. See text, (a) Formation of blanket pod oxide and Si N layer resist patterning (mask 1) ion implantation of channel stoppers (chanstop) (steps 1—3). (b) Growth of isolation field oxide removal of resist, Si N, and pod oxide growth of thin (<200 nm) Si02 gate oxide layer (steps 4—6). (c) Deposition and patterning of polysihcon gate formation of -source and drain (steps 7,8). (d) Deposition of thick Si02 blanket layer etch to form contact windows down to source, drain, and gate (step 9). (e) Metallisation of contact windows with W blanket deposition of Al patterning of metal (steps 10,11). The deposition of intermetal dielectric or final...

Conventional electronic devices are made on silicon wafers. The fabrication of a silicon MISFET starts with the diffusion (or implantation) of the source and drain, followed by the growing of the insulating layer, usually thermally grown silicon oxide, and ends with the deposition of the metal electrodes. In TFTs, the semiconductor is not a bulk material, but a thin film, so that the device presents an inverted architecture. It is built on an appropriate substrate and the deposition of the semiconductor constitutes the last step of the process. TFT structures can be divided into two families (Fig. 14-12). In coplanar devices, all layers are on the same side of the semiconductor. Conversely, in staggered structures gate and source-drain stand on opposing sides of the semiconductor layer. 

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