Floating point performance

In order to make a microcomputer, an attractive proposition for scientific work there must be some means of enhancing its floating point performance. There are multidudinous ways of achieving this and some of the possibilities will be discussed in increasing order of performance. 

The second possibility for improving microcomputer floating point performance lies with the North Star Hardware Floating Point Board (3). This device executes floating point, add, subtract, multiply and divide with up to twelve decimal digits of precision. One byte of data is reserved for the exponent and the other six for the mantissa of each floating point number. 

The remaining options for improving microcomputer floating point performance which will be considered lead to much higher performance than the Am9511A option but have one or more major drawbacks. 

On today s parallel computers communication is very slow compared to floating-point performance. It is sometimes possible to use multiple random number sequences to reduce the communication costs in a Monte Carlo simulation. An example occurs in our parallel-path integral calculations... 

A common acronym is MFLOPS, millions of floating-point operations per second. Because most scientific computations are limited by the speed at which floating point operations can be performed, this is a common measure of peak computing speed. Supercomputers of 1991 offered peak speeds of 1000 MFLOPS (1 GFLOP) and higher. 

A pipelined floating-point multiply unit might accomplish a floating-point multiply by performing four independent suboperations, labeled a, b, c, and d, on the operands. The suboperations can be envisioned as the four workers on a four-person assembly line. The floating-point multiply pipeline could accept a new set of operands every clock cycle. The pipeline occupancy of this code fragment would look like... 

At times you need to perform some form of floating-point number comparison. The following example illustrates such a comparison where you are setting laboratory value flags to indicate whether a lab test is above or below normal. 

You should read Technical Support Note TS-230 Dealing with Numeric Representation Error in SAS Applications to learn more about SAS floating-point numbers and storage precision in SAS. Another good resource for rounding issues is Ron Cody s SAS Functions by Example (SAS Press, 2004). In short, whenever you perform comparisons on numbers that are not integers, you should consider using the ROUND function. 

Solving the matrix equation Ax = b by LU decomposition or by Gaussian elimination you perform a number of operations on the coefficient matrix (and also on the right-hand side vector in the latter case). The precisian in each step is constrained by the precision of your computer s floating-point word that can deal with numbers within certain range. Thus each operation will introduce some round-off error into your results, and you end up with same... 

A block floating point technique (block companding) is used to quantize the subband samples. The calculation of scalefactors is performed every 12 subband samples. The maximum absolute value of the 12 subband samples is quantized with a quantizer step size of 2 dB. With 6 bits allocated for the quantized scalefactors, the dynamic range can be up to 120 dB. Only scalefactors for subbands with a non-zero bit allocation are transmitted. 

Floating Point. Integrated floating point units first arrived as separate coprocessors under the direct control of the microprocessor. However, these processors performed arithmetic with numerous sequential operations, resulting in performance too slow for real-time signal processing. 

The Zoran 38000 has an internal data path of 20 bits as well as a 20 bit address bus. The two accumulators have 48 bits. It can perform a Dolby AC-3 [Vernon, 1995] five channel decoder in real time, although the memory space is also limited to one Megaword. It has a small (16 instruction) loop buffer as well as a single instruction repeat. The instruction set has support for block floating point as well as providing simultaneous add and subtract for FFT butterfly computation. 

The TMS320C30 [Papamichalis and Simar, 1988] follows the basic architecture of the TMS-320 series. Unlike the DSP-32, it uses pipeline interlocks. Like the DSP-32, it features its own internal format for floating point numbers. Because of the four stage pipeline organization, it can perform a number of operations in parallel. It also features a delayed branch - something of a novelty in DSP processors. The TMS320C40 [Simar et al., 1992] has six parallel bidirectional I/O ports controlled by DMA on top of the basic TMS-320C30 architecture. These ports have been used for multiprocessor communication. 

The VAX used, is located at NRCC in Berkeley, has a floating point accelerator, 2.5 M Bytes of memory, and was running version 1.3 of the operating system. The code was run in single precision (32 bits/word) and that was found adequate to conserve energy and give satisfactory equilibrium properties. The code used to perform the pairwise sum is essentially that of Table I. 

Peripheral processors which are capable of performing floating point arithmetic operations at high speed are used to enhance the poor performance of popular general purpose minicomputers in this area. These devices are described in various ways but the following nomenclature will be used in this paper. 

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