Fault-Tolerant Software Techniques

Not a complete fault-tolerant software technique as it only detects errors. 

This paper addresses the issue of integrating already developed fault-tolerant (FT) techniques into software designs for their analysis through automatically... 

A common objective of such benchmarking is to measure the error sensitivity of a software component, and identify ways to harden the component against such errors by means of software-implemented hardware fault tolerance (SIHFT) techniques. 

Our future research will also encompass comparative studies with different compiler optimizations, hardware platforms, and different programming languages. Another important part of this work is to extend our study with experiments on target programs that are equipped with software-implemented hardware fault tolerance (SIHFT) techniques. 

Following the state-of-the-art review, the next step is to implement fault tolerance techniques. We will start by explaining in detail and implementing two known software-based techniques, called Variables and Inverted Branches (AZAMBUJA 2010b), which will later be used as a complement to hybrid fault tolerance techniques. These techniques have been proposed in the past years and achieved high fault detection rates at low performance degradation levels and therefore are useful not only as an introduction to software-based fault tolerance techniques, but also to be combined with hardware-based and hybrid techniques. Then, three novel hybrid techniques will be proposed and implemented, based on both software and hardware replication characteristics. The three hybrid techniques will be divided into their software and hardware sides and described in detail, concerning both operation description and implementation. 

The book is organized as follows Chap. 2 presents the terminology and general concepts used in this work. Chapter 3 describes existing fault tolerant techniques for processors presented in the literature. Chapter 4 describes the fault tolerant techniques implemented in this work to detect transierrt fairlts in processors, from which two are known software-based and three are new lybrid techniques. Chapter 5 presents experimental fault injection campaigns for the implemented fairlt tolerarrt techniques. Chapter 6 presents the configuration bitstream fairlt injection campaign and results. Chapter 7 presents radiation experiments on some of the proposed techniques. Chapter 8 describes future work and concludes the book. 

Although the effect of faults is increasing, the rate is not yet sufficient to test fault tolerant techniques at ground level. In order to do so, fault emulation and testing is necessary. In this Section, we will go over a few options to do so, such a software fault injection by simulation, fault injection in the FPGA s memory configuration bitstream and irradiation experiments. 

Fault tolerance techniques aiming to detect transient effects can be mainly divided in three broad categories (1) software-based techniques, (2) hardware-based techniques and (3) l brid techniques. Fault tolerance techniques can be applied at different levels of implementation, starting from the software level down to the architecture description level, the logical and transistor level, until the layout level. In this book, we will focus on hybrid techniques applied at software level. 

There are irmumerous means to reduce the risk of losing an AUV One could increase the vehicle reliability through redimdancy of critical components, use of safety barriers, at the hardware level. At the software level, software fault tolerance techniques, software diversity and formal checking are also techniques that can reduce the risk of system failure. At the operational level, a guided maintenance program is an effective way to reduce the risk. 

According to Savic (2008) Thus, if we wish to predict the reliabihty of a program in its operational environment, we need to base our predictions upon failure data collected when the software was operating in such an environment (or good simulated approximation of it). . In fact, to predict the reliability of the applied fault tolerance techniques, we need data regarding the behaviour of the system when real faults appear or realistic faults are simulated. 

The applied software fault tolerance techniques will be verified. Let us assume, for example, the implementation of the rule 20.3 by MisraC 2004 standard for critical systems. This rule indicates that the validity of values passed to library functions shall be checked to avoid errors. The fault injector can introduce a negative value before a sqrt function call to test the introduced value checking process and the consequences on the system if this check fails. 

The fault tolerant design discussed here mainly pertains to computing systems and intelligent systems for real-time computer systems such as DCS/PLC and/or associated intelligent devices. Here, the discussion is on the basics of hardware and software fault tolerant principles in computing systems, whereas that applicable to control systems is covered in Clause 1.2. Two ways in which fault tolerant designs can be developed are hardware technique and software technique. 

Because software fault tolerance is based on hardware fault tolerance, it is a bigger challenge. Additional software is used in computing systems for fault handling and for fault-free computation. A few major software fault tolerance techniques somewhat similar to their hardware counter parts have been... 

Hardware failure and software failure are two kinds of failures encountered in programmable systems, as already discussed. In cases of hardware failure, fault tolerant designs such as redundancy could be applied. Software failure, as discussed, has to overcome certain procedures, but certain failures (design failure) could include behaviors that can be unsafe. A new technique known as system theoretic process analysis is applied in nuclear installations. This is required to identify the control requirements and then check conditions caused hy inadequate control actions such as ... 

Petri-Net is a mathanatical model that describes the systan in graphical symbols. It is very useful for analyzing properties such as reachability, recoverability, deadlock, and fault tolerance. The biggest advantage of Petri-Nets, however, is that they can link hardware, software, and human elements in the system. The technique is also good for understanding software-timing issues in real-time systems. They can also be quantified with probabilities. 

This paper addresses some of the problems involved in the design of software for distributed processors, particularly where there are implications for safety. Modern software engineering techniques and languages are used to consider possible approaches to the design of such systems, and to discuss methods of providing fault tolerant structures for high reliability applications. 

Architecture-level fault injection (FI) has been the standard analysis technique in the software fault-tolerance community for at least two decades [8,9]. In an FI campaign... 

Safety engineers are now encouraged to use fault prevention techniques (e.g. through the publication of [MOD 91]), in particular the use of formal methods to the development of safety-critical software. To maximise the benefit of this approach the safety engineer would be wise to adopt the security principles of the "reference monitor concept" and security policy modelling. However, as in the case of security, the safety engineer would also be wise to utilise the more traditional safety engineering approach of fault tolerance in harmony with the new fault preventative approach. 

All systems need to be sufficiently reliable and secure in delivering the service that is required of them. Various ways in which this can be achieved in practice range from the use of various validation and verification techniques, to the use of software fault/intrusion tolerance techniques and continuous maintenance and patching once the product is released. Fault tolerance techniques range from simple wrappers of the software components [1] to the use of diverse software products in a fault-tolerant system [2]. Implementing fault tolerance with diversity was historically considered prohibitively expensive, due to the need for multiple bespoke software versions. However, the multitude of available off-the-shelf software for various applications has made the use of software diversity an affordable option for fault tolerance against either malicious or accidental faults. 

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