Etching aspect ratio

As with any other fabrication process, masks are needed to define the features to be etched. It is common that the etch used for the semiconductor also etches the masking material. For this reason many different masks are used in etching, including photoresist, dielectric films, and metals. Masking can be a complex issue, especially when very deep etches (>5 fim) are performed with high aspect ratios (148). 

There has been a continual increase in size and complexity of PCBs with a concurrent reduction in conductor and hole dimensions. Conductors can be less than 250 p.m wide some boards have conductors less than 75 pm wide. Multilayer boards greater than 2.5 mm thick having hole sizes less than 250 pm are being produced. This trend may, however, eventually cause the demise of the subtractive process. It is difficult to etch such fine lines using 35-pm copper foils, though foils as thin as 5 pm are now available. It is also difficult to electroplate holes having high aspect ratio. These factors may shift production to the semiadditive or fully additive processes. 

Similar to prepared metallographic samples, the injection molded samples were cut along the flow direction, smoothed, and polished in order to expose their internal surface. After proper etching, the treated surfaces of the flank cross-section were photographed using a polarized light optical microscopy. Based on the color differences between the TLCP and matrix, volume fraction and aspect ratio of the TLCP fibers were measured [23]. 

Anisotropic etching (i.e. etching of bulk material with etch rates depending on material/crystal orientation, used in single crystal material in order to determine clear features and geometry aspect ratios). 

For good aspect ratio and device geometry, anisotropic etching agents have to exhibit a strong difference in etch rate between crystal directions. In a typical KOH solution for single crystal Si, about a two orders of magnitude smaller etch rate in... 

The development of low-dielectric-constant materials as ILDs is crucial to achieve low power consumption, reduce signal delay, and minimize interconnect cross-talk for high-performance VLSI devices. In one of the multilevel interconnect process routes, metal lines (e.g., A1—Cu or Cu) are patterned through reactive ion etching, and then dielectric films are filled in the trenches formed between these lines. These trenches can have widths in the sub-0.5 pm range and aspect ratios greater than 3. Therefore, small gap-filling capability is also required for such dielectrics. 

In conclusion it can be said that the limits of macropore array formation are in some way complementary to the limitations of plasma etching [Ja3]. The latter technique gives a higher degree of freedom in lateral design, while the freedom in vertical design and the feasible pore aspect ratios are limited. 

In this chapter, the motivations to adopt MLR systems for optical e-beam, x-ray, and ion-beam lithographic systems will be given, followed by a survey of published MLR systems. Specific practical considerations such as planarization, pinhole and additive defects, interfacial layer, etch residue, film stress, interference effects, spectral transmission, inspection and resist stripping will be discussed. The MLR systems will be compared in terms of resolution, aspect ratio, sensitivity, process complexity and cost. 

A high aspect ratio pattern can be obtained because the bottom layer is etched by a reactive ion etching 02 plasma (02 RIE) where the etching takes place anisotropically. 

With the two layer resist process, no effect of the surface structure is observed in the resulting resist pattern. A 0.35 wide lines with an aspect ratio of 6 have almost vertical side-walls and show a linewidth loss less than 0.1 iim by the etching of 2.0 thick AZ layer. In spite of the thin film of SNR, pin-holes were hardly observed in the dry-etched AZ patterns, presumably due to good wettability of silicone resin on organic film surface. 

A new silicone-based negative resist (SNR) for two layer resist systems was designed and prepared. It showed excellent dry etching durability to 02 RIE, high sensitivity to electron beam, X-ray and deep UV, and high resolution. Two layer resist with SNR/AZ resist is very effective to achieve submicron patterns with high aspect ratio, and will be used for the fabrication of submicron patterns over topography such as the metallization of electrode patterns in the last step of VLSI fabrication process. 

Feature Sizes. Although minimum feature sizes in TFML interconnections are large relative to IC feature sizes (i.e., 25- xm versus l- xm line widths), the conductor and dielectric layers are substantially thicker in TFML structures, a fact that results in high aspect ratios. Conductor layers must be several micrometers thick to keep resistive losses low, and dielectric layers must be 10 to 30 xm thick to maintain low interconnection capacitance. Thus a thickness width aspect ratio as large as 1 1 is frequently required. This aspect ratio demands anisotropic-etching processes. 

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