Dielectric fabrication process

As with any other fabrication process, masks are needed to define the features to be etched. It is common that the etch used for the semiconductor also etches the masking material. For this reason many different masks are used in etching, including photoresist, dielectric films, and metals. Masking can be a complex issue, especially when very deep etches (>5 fim) are performed with high aspect ratios (148). 

During the fabrication process the surface of the semiconductor is etched and metal contacts are deposited. These features can represent a topographical challenge to subsequent metal wiring levels. For this reason it is important that the dielectric film used tends to smooth out such discontinuities as metal and etched edges (150,217). Additional appHcations for spin-on dielectrics include forming integrated microlenses for optoelectronics (218). 

Ferroelectric Thin-Film Devices. Since 1989, the study of ferroelectric thin films has been an area of increasing growth. The compositions studied most extensively are in the PZT/PLZT family, although BaTiO, KNbO, and relaxor ferroelectric materials, such as PMN and PZN, have also been investigated. Solution deposition is the most frequentiy utilized fabrication process, because of the lower initial capital investment cost, ease of film fabrication, and the excellent dielectric and ferroelectric properties that result. 

Since the end of the 1970s, the polyimides have been introduced for the production of electronic components mainly for the passivation. But more and more they are interesting for the integrated circuits and multichip modulus fabrications. Processability and dielectric and thermomechanical properties are the most attractive features of these materials for the electronic31 and electro-optical applications.32... 

A cross-sectional schematic of a monolithic gas sensor system featuring a microhotplate is shown in Fig. 2.2. Its fabrication relies on an industrial CMOS-process with subsequent micromachining steps. Diverse thin-film layers, which can be used for electrical insulation and passivation, are available in the CMOS-process. They are denoted dielectric layers and include several silicon-oxide layers such as the thermal field oxide, the contact oxide and the intermetal oxide as well as a silicon-nitride layer that serves as passivation. All these materials exhibit a characteristically low thermal conductivity, so that a membrane, which consists of only the dielectric layers, provides excellent thermal insulation between the bulk-silicon chip and a heated area. The heated area features a resistive heater, a temperature sensor, and the electrodes that contact the deposited sensitive metal oxide. An additional temperature sensor is integrated close to the circuitry on the bulk chip to monitor the overall chip temperature. The membrane is released by etching away the silicon underneath the dielectric layers. Depending on the micromachining procedure, it is possible to leave a silicon island underneath the heated area. Such an island can serve as a heat spreader and also mechanically stabihzes the membrane. The fabrication process will be explained in more detail in Chap 4. 

The TFT fabrication process on glass substrates starts with 100 nm of Cr for the gate metal, and is followed by a PECVD 200 nm thick Si3N4 dielectric with a 30 nm thick SiC>2 surface layer. The source drain metal is Cr/Au. Each of these layers is patterned using printed wax masks and chemical etching, steps a to d in Fig. 11.8. The surface is modified with a solution deposition of a self-assembled monolayer of octyltrichlorosilane (OTS-8) before inkjet printing deposition of the semiconductor. It has been shown that the OTS-8 layer affects the structural order of PQT-12 in thin films, improving the performance of the TFT [23]. Encapsulation and possibly other subsequent layers may be needed on the TFT, but these are not discussed here. 

These developments have only been possible because of a continuing improvement in understanding of the basic solid state science of the ceramic dielectrics, of the electrode metals and of the interaction between the two, and particularly of the technologies of ceramic powder production and the MLCC fabrication processes. 

In this section, we review the present manufacturing processes and discuss the challenges facing the extendability of these processes to the new generation of IC products. There are three primary fabrication processes (1) metal-reactive ion etching (RIE), (2) dielectric RIE, or damascene, and (3) through-mask deposition process. 

The change from Al to Cu interconnects required a change in the fabrication process from metal RIE to dielectric RIE since it is difficult to pattern Cu by RIE [98]. 

Multilevel Cu interconnections on chips are now fabricated using a dielectric-RIE process. In this process, a blanket Cu deposition is followed by chemical-mechanical polishing (CMP) of Cu [99], This approach... 

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