Create netlist

Next, we will look at the netlist created by this hierarchical design. Select PSpice and then Create Netlist from the Capture menus to create the netlist, and then select PSpice and then View Netlist to display the netlist ... 

Note in the above right screen capture that the text MEH OpAmp is selected. If the subcircuit name is not selected, click the LEFT mouse button on the text to select it. We can now create the subcircuit netlist. Select Tools and Create Netlist from the Capture menus ... 

To check for errors, select PSpice and then Create Netlist ... 

The value of the PSpICe Template property generates the PSpice netlist line for the resistor when you create a netlist for the schematic. The TC property is a temperature coefficient for the resistor. Its default is zero (no temperature dependence). The property Value is the value of the resistor in ohms. The Source Library (not shown in the screen captures above) is the name of the. olb file in which the part is located. 

The Reference is set to BLKl. This is similar to a part name such as R1 or C3 except that the reference will affect how nodes and parts within the block are named. For example, a resistor within BLKl named R1 on the schematic would be referred to as R BLK1 R1 in the PSpice netlist. A node labeled as vo in block 1 will be renamed as BLKl vo if that node does not connect to components inside another block. An Implementation Type of Schematic View was chosen because we will create the contents of the block using OrCAD Capture. You can also specify the function of a block using other methods such as writing a VHDL description of the block (not available in Oread Lite). The Implementation Name will become the name of the folder in the project tree where the schematic is located. When we look at the tree view... 

We are now ready to simulate the circuit. Select PSpice from the menu bar and then select Run. Capture will first create an updated netlist and then run PSpice. When the simulation is complete, the Probe window will display an empty plot ... 

There are two properties that display the name of the model, the Value property and the Implementation property. The Value property is not used by PSpice, but this property is sometimes displayed on the schematic instead of the PSpice model name. The Implementation property is the name of the PSpice model and it is the property used when creating the netlist. If you change the Value property to the name of your new model, nothing will change in the simulation. If you change the Implementation property to the name of your new model, the new model will be used. Always change the Implementation property. 

We are now ready to create the subcircuit netlist for this circuit. Select File and then Save to save the circuit, and then select File and then Close to close the window. You should return to the project tree for this circuit. Expand all the branches of the tree ... 

Make sure that the path and filename are entered correctly in the box. When the settings are correct, click the OK button to create the subcircuit netlist. After a few moments, the netlist will be created and a window will open and display the netlist ... 

This netlist describes the circuit we created in Capture. Since we chose to create a subcircuit netlist, the second line of the file declares the netlist as a subcircuit. The name of the subcircuit is MEHjOpAlTip, or whatever you named your subcircuit, and the calling nodes are Vm, V0, and Vp. These node names were derived from the ports we added to the circuit. The order is not important because we will have Capture create the symbol for this subcircuit, and it will use the same nodes in the correct order. 

In the previous section, we created the netlist for our subcircuit. Next, we have to create a graphic symbol to place in our schematic. We will continue with the previous example where we are displaying the project tree. Note that the subcircuit name is still selected ... 

In the NetllSt file field, enter the name of the netlist we created in the previous section. You can use the Browse button to select the file we created. I named my netlist file C Program Files OrcadLite Capture Library PSpice User subcircuits.lib. 

This appendix contains a brief discussion of the common errors encountered in drawing schematics. There are two types of errors you may encounter when you use Oread Capture with PSpice. The first type are drawing errors, which are detected by the Capture program. When you create a netlist, any drawing errors will be detected by Capture and the circuit will not be simulated. Thus, all drawing errors must be corrected before the circuit can be simulated. 

Creating a netlist performs an electrical rule check, so we shall attempt to create a netlist. Errors are indicated by the dialog box and on the circuit by the presence of the green washers. Click the OK button to close the dialog box. 

We now check the circuit again by creating a netlist. Once again there are errors ... 

No more errors will be indicated when we create a netlist. However, there are still two errors in the drawing. The first is that the circuit is not grounded. The entire circuit is floating. This error would have been caught when we ran the simulation. You must add a part called 0 to your circuit. Select Place and then Power from the Capture menus to place the ground. 

Note that the synthesis directory is created by FPGA Express to hold its project file synthesis.exp as well as our synthesized hardware (netlist file . edf ). 

Electrical Test Programs and Fixture Creation. An electrical test netlist file may be either created internally from the artwork or prepared from a supphed IPC-D-356 file. This test file has to be compared to the nethst extracted from the artwork supphed. Any difference must be resolved before the actual electrical test file is finalized. In addition, the electrical test fixture must be constructed or sent to an outside contractor to prepare. 

To perform gate level simulation of a VHDL netlist one requires the VHDL simulation libraries from the ASIC vendor. The Synopsys liban utility can generate the VHDL library models from the synthesis technology library. For tiie more complex cells, simulation models will have to be manually created. The VHDL models generated are encrypted so that the vendor proprietary information is protected. 

Create a translation library for these black-box cells. For example, if your netlist has a black-box cell mem and your targetjibrary contains an equivalent cell mem new, then create a translation library which is essentially a module that instantiates the target cell mem new, but with the same interface as the mem cell as shown in Example 5.3. 

Clock pads should normally be inserted only for the ports with a clock object created on it. However, they might be inserted on other ports if those ports are part of clock gating logic. If the pads are being inserted on a compiled netlist that contains clock enable buffers, then those ports coimected to the clock enable buffers may have clock pads inserted on them also. For other regular inputs, clock pads should not be used. This problem can be avoided by specifying the set pad type -no clock attribute on all inputs, except the clock input, prior to pad insertion. 

You execute insert scan at the core level of your design followed by check test. TC report no errors. Then you create another hierarchy around your core design and manually instantiate pads. On executing check test at the top level of the design with the pads included in the netlist, TC reports, No scan-path found . 

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