Nodes labels

The constraint transformation algorithm accepts a network of goals partially ordered by constraints, and generates a constraint network of primitive actions, such that, if there exists a directed path from goal A to goal B (i.e., A must be achieved before B) in the first network, and if OP-A is the primitive action that achieves goal A, and OP-B the action that accomplishes B, then OP-A and OP-B are labels on nodes in the generated network, and there exists a directed path from the node labeled with OP-A to the node labeled with OP-B. 

Any node, v, which is on a directed path from any source, is labeled with x. Let A, be the set of nodes labeled with x, and let E be the set of associated edges. Nodes labeled with x, and tht attached edges contain the chemical species. 

The definition of a block given here is really a bottom-up definition, building large blocks fran smaller subblocks. When one actually constructs a block structured program, one proceeds top-down - first defining the role of the outermost block (what process it is to realize), then that of its immediate subblocks, and so forth. A single node (labelled by a process for which one intends to build a submodule) can be considered a block. The equivalence of the top-down and bottom-up definitions can be justified by the block replacement lemma, stated without proof. 

The scheme in P in Example IV-2 is not tree-like. (Here we let A,B,C,D,E stand for arbitrary assignment statements or sets of assignment statements, in order to exhibit the structure of the example uncluttered by extraneous formulae.) The direct connection from the node labelled T(x ) following the node labelled D up to the node labelled B is anomalous since the path START A T(x ) D T(x ) does not contain B and the path START A T(x- ) B does not contain the node labelled T(x- ) following D. Similarly the two direct connections at the bottom of the diagram, from test T(x2) to test T(x ) and from test T(x ) to E are anomalous. The other direct connections in the graph are not anomalous. For example, the direct connection from test T(x2> up to the node labelled A is not anomalous since A is an ancestor of every node in the graph except START. 

Scheme P is a graph hononorphic image of the scheme P in Example IV-3, which is tree-like. Scheme P is formed from P by duplicating nodes when anomalous connections occur. Thus the direct connection from the node labelled T(x ) which follows D, to B is anonalous in P. In P, this connection is removed and a direct connection to a copy of B is substituted. The copy of B leads into a copy of the subscheme reachable from B until A occurs. We do not need to duplicate A since any connection to A must be acceptable hence the diagram loops lack to A. Similarly, the anomalous direct connection from the node T(x ) which follows C to E is anonalous and is replaced by a connection to a copy of E and the node following E, TCxg) the connections from this instance of I(x2) are now legal and so no duplicates are needed.

We can represent an expanded term as a tree in the obvious fashion. A variable or constant is represented by a single node labelled by itself ... 

The Reference is set to BLKl. This is similar to a part name such as R1 or C3 except that the reference will affect how nodes and parts within the block are named. For example, a resistor within BLKl named R1 on the schematic would be referred to as R BLK1 R1 in the PSpice netlist. A node labeled as vo in block 1 will be renamed as BLKl vo if that node does not connect to components inside another block. An Implementation Type of Schematic View was chosen because we will create the contents of the block using OrCAD Capture. You can also specify the function of a block using other methods such as writing a VHDL description of the block (not available in Oread Lite). The Implementation Name will become the name of the folder in the project tree where the schematic is located. When we look at the tree view... 

We see that both nodes labeled Vref are at a voltage of 10.01 volts. The negative feedback attempts to keep these two voltages the same. The emitter current is 1.001 mA and the collector current is 997 XA. Since Ic = [P/(P+1)]Ie, we expect the collector current to be slightly less than 1 mA, in this case 3 pA. 

Node label Current-controlled voltage source ... 

DC voltage source lf411 Operational amplifier Node label... 

Node label Node label Ideal XFMR Vo/Vin D1N5401... 

Instead of a node label, such as a bubble, having been placed on the ClOCh wire, the wire has been labeled. To label a wire, select Place and then Net Alias from the menus. A dialog box will appear, asking you for a label. Enter a name for the label and then place the label next to a wire. It is sometimes better to label a wire rather than add a bubble, because a bubble adds more clutter to a circuit drawing. 

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