Netlist line

The value of the PSpICe Template property generates the PSpice netlist line for the resistor when you create a netlist for the schematic. The TC property is a temperature coefficient for the resistor. Its default is zero (no temperature dependence). The property Value is the value of the resistor in ohms. The Source Library (not shown in the screen captures above) is the name of the. olb file in which the part is located. 

This netlist describes the circuit we created in Capture. Since we chose to create a subcircuit netlist, the second line of the file declares the netlist as a subcircuit. The name of the subcircuit is MEHjOpAlTip, or whatever you named your subcircuit, and the calling nodes are Vm, V0, and Vp. These node names were derived from the ports we added to the circuit. The order is not important because we will have Capture create the symbol for this subcircuit, and it will use the same nodes in the correct order. 

The first line of any SPICE netlist is the title line. It is used for documentation purposes only. The next few lines usually tell SPICE which analysis will be performed and what the bounds of that analysis will be. For example, we may be requesting a time domain analysis of a circuit (called a transient analysis). The information as to how long the waveform is and what increments and what section of it are of interest is defined in this section of the code. SPICE netlists generally have one function, command, or element per line (Fig. 2.1). Also defined upfront are global constants, subcircuits (models) used repeatedly in the main circuit, and instructions on which nodes are of interest in the final solution, though this structure is not mandatory. 

Figure 2.1 Typical lines of the beginning of a SPICE netlist.

From this example, it appears that all the inputs to NextState, the value 12, the value 5, and the variable CurrentState, should be multiplexed using appropriate select lines into the D-input of the inferred flip-flops for Next-State. This is exactly what occurs as shown in the synthesized netlist in Figure 2-55. So then, how can we infer flip-flops with synchronous preset and clear A synthesis system may provide a solution for this by providing a special option for directing the synthesis system to generate a synchronous preset clear flip-flop. 

FIGURE 18.7 Example of a netlist (a) this part represents a physical netlist with X and y coordinates (the first line translates as Kn U5 of component IC52 is connected to net LDIN 47 and is at location [11.0078, 3.0997] (b) this part represents the same netlist but at schematic stage with only component and pin names the electric signal identified as LDIN 47 connects IC52 pin V5 to ICIO pin J2 through two vias. 

In this synthesis, the amount of output data (23,640 lines in netlist) is 19 times larger than the input data (1,229 lines in SFL). Using a conventional method, it would take from 200 to 400 man-days to design a processor such as the FDDP. Such an effort would be from 13 to 25 times larger than that required using PARTHENON to carry out the same design. Since the order of difference of data size and design effort are equivalent, it can be said that this FDDP is not an exceptional case. 

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