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In-place optimization

The most crucial factor in the IPO process are the values and attributes on cells in the technology libraiy. All cells that can be swapped must have footprints attached to them. DC swaps only those cells that have the same foo rint. This behavior can be controlled by dc shell compile variables. The more the number of cells with the same footprint, the greater the choice of cells available to DC. One must ensure that swappable cells do not have dont touch or dont use attributes set on them in the library. [Pg.187]


After performing an initial place and route, you have available accurate load values on the nets in the design. You specify these loads on the appropriate nets in the design using a setjoad dc shell script. You then perform in-place optimization, but find that... [Pg.151]

DC does not seem to consider the new load specified on that net and appropriately size the driver cell. For example, in Figure 5.6, you expect DC to use a higher drive AND gate after in-place optimization. [Pg.152]

At this point, the timing violations, if any, should be fixed by performing in place optimization on the design using the reoptimize design -ipo command as discussed in section 6.5. [Pg.178]

Example 6.4 shows net resistance and net parasitic file written out from a commercial Florrplanning tool. In other words, the tool provides estimated resistance and capacitance values for each net in the design. This information can be back-annotated to DC to generate new more accurate wire load models as discussed in section 6.4 or to perform in place optimization. [Pg.184]

Perform in-place optimization, (reoptimize design -in placc -map cffort high)... [Pg.189]

After performing in-place optimization a few times (that is, repeating step 13), no further swapping will be possible and the swap-cells file will show no additional swaps. DC appends the list of cells to the swap-cells file each time a compile is performed and does not overwrite the existing file. [Pg.189]

This script does the following to modify the Synopsys library for in place optimization. [Pg.304]

If you remove the library from DC memory for some reason, be sure to include this script again. This will ensure that you are using the library for in place optimization. [Pg.304]

For in place optimization, often back annotated information after P R is in the form of set load script. After including these set load information, it might be required to find all the nets which have load values set and all the nets which do not. Then for all those without load values, it might be required to set specific load value. The following script can be used to do this. [Pg.307]

Chapter 6 is devoted to Links to Layout. What are the mechanisms available for links from front-end tools like Design Compiler to backend tools such as floor-planning and place and route tools How does one perform in-place optimization This chapter addresses these and similar issues relating to links between Synopsys logic synthesis tools and back-end tools using the Synopsys Floorplan Manager. [Pg.338]


See other pages where In-place optimization is mentioned: [Pg.96]    [Pg.3]    [Pg.12]    [Pg.131]    [Pg.186]    [Pg.186]    [Pg.186]    [Pg.187]    [Pg.187]    [Pg.187]    [Pg.188]    [Pg.188]    [Pg.96]   
See also in sourсe #XX -- [ Pg.187 ]




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In place Optimization Steps

Places

Placing

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