ASIC synthesis

Computer-aided synthesis of digital circuits from an algorithmic description is a difficult problem. We have proposed in this research an approach to ASIC synthesis that addresses some of the difficulties in effectively integrating a synthesized design with other components in the system. However, many difficult problems have not yet been solved. We summarize in Section 12.1.1 the... 

Kellard B., Clifford M.N. and Birch G.G. (1988) Progress in the chemical synthesis and organoleptic evaluation of chlorogenic acids. 12th. Int. Colloq. Chem. Coffee (Montreux, 29. 6-3.7.1987) (ASIC, 1988), 254-9. 

Economakos, G, P akonstantinou, G and Tsanakas, P. (1997) Attribute Grammar Driven Scheduling for the Hgh-Level Synthesis (d ASICs. submitted to 1997 lEEE/ACM International Conference on Conputer Aided Design. 

Paulin, P. G and Knight, J. P. (1989) Force-Directed Scheduling for the Behavioral Synthesis of ASICs. IEEE Transactions on Computer-Aided Design, Vol 8, No 6, pp 661-679. 

D. Ku and G. De Micheli. Synthesis of ASICs with Hercules and Hebe. In R. Camposano and W. Wolf, editors. Trends in high-level synthesis. Kluwer, Boston, 1991. 

M. van Swaaij, J. Rosseel, F. Catthoor, and H. De Man. Synthesis of ASIC regular arrays for real-time image processing systems. In E. Deprettere et al., editors, Algorithms and Parallel VLSI Architectures, Vol. B, pages 329-342, Elsevier Science, 1991. 

The intention of this section is to give a brief overview on the whole framework, since the remainder of this chapter will focus exclusively on a single aspect, namely the automatic synthesis of a behavioral specification down to the ASIC emulator board. If the emulation demonstrates that an overall performance increase will be obtained through the realization of corresponding system submodules by an ASIC, other synthesis tools (such as Cathedral or Amical, described in chapters 7 and 9) have to be used to derive a final chip solution replacing the emulator. 

Structural synthesis comprises another group of transformations to be executed on the submitted flow graph. The main tasks to be solved are scheduling, allocation, and binding. The flow graph format cannot be maintained during those steps, since more and more structural information will be derived. The final output after structural synthesis will be all information necessary to customize the ASIC emulator board. 

All the synthesis steps mentioned above can be executed either automatically or interactively. The programmed ASIC emulator can be inserted directly into the overall mechatronic system to facilitate real-time test runs. In the following, all main synthesis steps will be described in the same top-down sequence as they are implemented through the synthesis script. Throughout the rest of the chapter, the terms ASIC emulator (board), rapid prototyping board, and target architecture will be used synonymously. 

The application domain and ASIC emulator architecture strongly influence the overall synthesis script as well as the actual algorithms for solving single synthesis tasks. In order to achieve efficient solutions, our whole approach has been tuned toward real-time system applications as they are found in mechatronic systems. To support the understanding of the implemented approach/algorithms, this section will describe the intended application domain and ASIC emulator architecture in more detail. 

After behavioral synthesis, a transformed and optimized flow graph is available, which still does not include any explicit structural information (except module-type proposals for background memory and constraints specified in the input description). The goal of the consecutive structural synthesis process is to transform this flow graph information into an actual implementation that can be executed on the ASIC emulator board. The main steps to be carried out are scheduling, allocation, and binding. The results will again be illustrated by means of the DHRC-benchmark. 

P. Pochmiiller and M. Glesner. Memory management as a high level synthesis transformation. In ASIC 92, Rochester, pages 166-169, Sep 1992. 

P. Paulin and J. Knight. Force-directed scheduling for the behavioural synthesis of ASICs. IEEE Transactions on CAD of Integrated Circuits and Systems, CAD-8, number 6, pages 661-679, Jun 1989. 

HIGH LEVEL SYNTHESIS OF ASICs UNDER TIMING AND SYNCHRONIZATION CONSTRAINTS, D. C. Ku, G. De Micheli ISBN 0-7923-9244-2... 

We empirically validate proposed transformations and the entire RUMBLE flow. We show how these techniques can be used to significantly improve initial latch placement in a reasonably optimized ASIC design. Our do-no-harm acceptance criteria reject solutions if any quality metrics are degraded. This key feature facilitates the use of RUMBLE later in physical synthesis. 

Achieving timing closure for large modern ASIC designs requires the use of physical synthesis—a series of performance-driven optimizations that simultaneously alter the layout, the netlist and electrical parameters of logic gates. 

Silicon compilers, synthesis tools Software programs that can construct an ASIC whose functionality is no longer described by a circuit schematic but in a special high level computer languages, generally called hardware description languages or HDL. 

Pierre G. Paulin and John P. Knight, Force-Directed Scheduling for the Behavioral Synthesis of ASIC s , IEEE Trans, on CAD, pages 661-679, June 1989. 

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